rcvr_old.v

使用Verilog语言编写

`timescale 1 ns / 100ps

module rcvr ( clk,rst,rxd,baud_clk,baud_clk1,
              fifor_cs,
              data_out,EF,AE,AF,FF,rbr) ;  //接收模块

input clk,rst ;
input baud_clk,baud_clk1;
input fifor_cs;
input rxd ;  //接收串口数据

output [7:0] data_out; //输出到8位总线
output EF,AE,AF,FF;
output [7:0] rbr;
reg rxd1,rxd2 ;
reg baud_clk_enable ;
reg [7:0] rsr ; //
reg [3:0] no_bits_rcvd ;//顺序控制计数器

wire baud_clk ;
wire [7:0] data_out1;
reg [7:0] data_out;

reg wr; 
reg tmp;
reg pop;
always @(posedge clk ) tmp = fifor_cs;

always @(posedge clk ) pop = !fifor_cs & tmp & !EF; //保护FIFO不会溢出错误

always @(posedge clk ) if(pop) data_out <= data_out1 ;

UART_FIFO u1( .clk( clk ),
              .rst( rst ),
		      .data_in( rbr ),
		      .data_out( data_out1 ),
		      .push( wr ),
		      .pop(pop),
		      .EF( EF ),
		      .AE( AE ),
		      .AF( AF ),
		      .FF( FF )
		    );

always @(posedge clk or posedge rst)
begin	 if (rst)	 begin
                         rxd1 <= 1'b1 ;     
                         //rxd2 <= 1'b1;
                         end
         else 	     begin
                     rxd1 <= rxd ;  //延一拍
                     //rxd2 <= rxd1 ;
                     end
        
 end

always @(posedge clk or posedge rst)	   
       if (rst)	      baud_clk_enable <= 1'b0;
           else if (rxd1 && !rxd)   baud_clk_enable <= 1'b1 ; //串口接收开始标志位 rxd 下降沿
                else if (no_bits_rcvd == 4'b1011)  baud_clk_enable <= 1'b0 ;//标志位产生后至少维持10个周期 一次串口接收结束 

reg state1 ;
reg [7:0] rbr;

always @(posedge baud_clk or posedge rst)
if (rst)    begin
            rsr <= 8'b0 ;
            rbr <= 8'b0 ;
			state1 <= 0 ;
			end
else        begin    if ( (no_bits_rcvd >= 4'b0001) & (no_bits_rcvd <= 4'b1001) )   //1-8拍			    
                     begin
					 //case(state1) 
					 //0  :  if(baud_clk) begin
                                        rsr[7] <= rxd ;  //串入数据
                                        rsr[6:0] <= rsr[7:1] ;
 					//	                state1 <= 1;
                                        //end
					 //1  :  if(!baud_clk) state1 <= 0 ;
					 //endcase
                     end
                     else if(no_bits_rcvd==4'b1010) rbr <= rsr;
			end

reg state ;

always @(posedge clk or posedge rst)
  if(rst)  begin 
           state <= 0;
           wr <= 0;
		   end
  else     begin
           case(state)
		   0 : if( (no_bits_rcvd == 4'b1010) && !FF ) begin
		                                              wr <= 1;
				                                      state <= 1 ;
 				                                      end
           1 : begin
		       wr <= 0 ;
               if( no_bits_rcvd == 4'b0000) state <= 0;
			   end
           endcase
           end
///////////////////
always @(posedge baud_clk or posedge rst or negedge baud_clk_enable)
       if (rst)	
	         no_bits_rcvd = 4'b0000;
       else  if (!baud_clk_enable)  
	         no_bits_rcvd = 4'b0000 ;
        else	   
	         no_bits_rcvd = no_bits_rcvd + 1 ;

endmodule