colorbar.vo

verilog源代码

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "04/01/2006 12:16:08"

// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ColorBar (
	rst,
	clk,
	VGA_HS,
	VGA_VS,
	VGA_RGB);
input 	rst;
input 	clk;
output 	VGA_HS;
output 	VGA_VS;
output 	[2:0] VGA_RGB;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ColorBar_v.sdo");
// synopsys translate_on

wire \inst4|altpll_component|_clk1 ;
wire \inst4|altpll_component|_clk2 ;
wire \inst4|altpll_component|_clk3 ;
wire \inst4|altpll_component|_clk4 ;
wire \inst4|altpll_component|_clk5 ;
wire \clk~combout ;
wire \inst4|altpll_component|_clk0 ;
wire \rst~combout ;
wire \inst|hcnt[0] ;
wire \inst|hcnt[0]~517 ;
wire \inst|hcnt[0]~517COUT1_561 ;
wire \inst|hcnt[1] ;
wire \inst|hcnt[1]~529 ;
wire \inst|hcnt[1]~529COUT1_562 ;
wire \inst|hcnt[2] ;
wire \inst|hcnt[2]~533 ;
wire \inst|hcnt[2]~533COUT1_563 ;
wire \inst|hcnt[3] ;
wire \inst|hcnt[3]~537 ;
wire \inst|hcnt[3]~537COUT1_564 ;
wire \inst|hcnt[4] ;
wire \inst|hcnt[4]~525 ;
wire \inst|hcnt[5] ;
wire \inst|hcnt[5]~545 ;
wire \inst|hcnt[5]~545COUT1_565 ;
wire \inst|hcnt[6] ;
wire \inst|hcnt[6]~541 ;
wire \inst|hcnt[6]~541COUT1_566 ;
wire \inst|hcnt[7] ;
wire \inst|hcnt[7]~549 ;
wire \inst|hcnt[7]~549COUT1_567 ;
wire \inst|hcnt[8] ;
wire \inst|LessThan~4981 ;
wire \inst|hcnt[8]~553 ;
wire \inst|hcnt[8]~553COUT1_568 ;
wire \inst|hcnt[9]~521 ;
wire \inst|hcnt[10] ;
wire \inst|LessThan~4997 ;
wire \inst|hcnt[9] ;
wire \inst|LessThan~4995 ;
wire \inst|LessThan~4976 ;
wire \inst|LessThan~4994 ;
wire \inst|hsyncint ;
wire \inst|vcnt[0] ;
wire \inst|vcnt[0]~453 ;
wire \inst|vcnt[0]~453COUT1_469 ;
wire \inst|vcnt[1] ;
wire \inst|vcnt[1]~457 ;
wire \inst|vcnt[1]~457COUT1_470 ;
wire \inst|vcnt[2] ;
wire \inst|vcnt[2]~449 ;
wire \inst|vcnt[2]~449COUT1_471 ;
wire \inst|vcnt[3] ;
wire \inst|vcnt[3]~461 ;
wire \inst|vcnt[3]~461COUT1_472 ;
wire \inst|vcnt[4] ;
wire \inst|vcnt[4]~445 ;
wire \inst|vcnt[5] ;
wire \inst|vcnt[5]~465 ;
wire \inst|vcnt[5]~465COUT1_473 ;
wire \inst|vcnt[6] ;
wire \inst|vcnt[6]~441 ;
wire \inst|vcnt[6]~441COUT1_474 ;
wire \inst|vcnt[7] ;
wire \inst|vcnt[7]~437 ;
wire \inst|vcnt[7]~437COUT1_475 ;
wire \inst|vcnt[8] ;
wire \inst|LessThan~4990 ;
wire \inst|vcnt[8]~433 ;
wire \inst|vcnt[8]~433COUT1_476 ;
wire \inst|vcnt[9] ;
wire \inst|always5~9490 ;
wire \inst|LessThan~4998 ;
wire \inst|LessThan~4999 ;
wire \inst|vcnt[9]~425 ;
wire \inst|vcnt[10] ;
wire \inst|always3~124 ;
wire \inst|always3~125 ;
wire \inst|LessThan~4980 ;
wire \inst|always5~9491 ;
wire \inst|vsync ;
wire \inst|always5~9476 ;
wire \inst|always5~9501 ;
wire \inst|always5~9502 ;
wire \inst|LessThan~4982 ;
wire \inst|LessThan~4978 ;
wire \inst|LessThan~4983 ;
wire \inst|always5~9503 ;
wire \inst|LessThan~4984 ;
wire \inst|always5~9438 ;
wire \inst|always5~9436 ;
wire \inst|always5~9494 ;
wire \inst|always5~9504 ;
wire \inst|always5~9480 ;
wire \inst|always5~9485 ;
wire \inst|always5~9486 ;
wire \inst|always5~9482 ;
wire \inst|always5~9456 ;
wire \inst|always5~9481 ;
wire \inst|always5~9483 ;
wire \inst|always5~9484 ;
wire \inst|always5~9487 ;
wire \inst|LessThan~4979 ;
wire \inst|always5~9489 ;
wire \inst|always5~9492 ;
wire \inst|always5~9488 ;
wire \inst|always5~9493 ;
wire \inst|always5~9497 ;
wire \inst|always5~9498 ;
wire \inst|always5~9499 ;
wire \inst|always5~9495 ;
wire \inst|always5~9451 ;
wire \inst|always5~9496 ;
wire \inst|always5~9500 ;
wire \inst|pixel[1]~558 ;
wire \inst|always5~9439 ;
wire \inst|always5~9518 ;
wire \inst|always5~9519 ;
wire \inst|LessThan~4996 ;
wire \inst|LessThan~4985 ;
wire \inst|LessThan~4986 ;
wire \inst|always4~81 ;
wire \inst|enable ;
wire \inst|always5~9446 ;
wire \inst|always5~9445 ;
wire \inst|always5~9447 ;
wire \inst|always5~9452 ;
wire \inst|always5~9453 ;
wire \inst|always5~9444 ;
wire \inst|always5~9449 ;
wire \inst|always5~9448 ;
wire \inst|always5~9450 ;
wire \inst|always5~9454 ;
wire \inst|always5~9441 ;
wire \inst|always5~9442 ;
wire \inst|always5~9440 ;
wire \inst|always5~9443 ;
wire \inst|LessThan~4975 ;
wire \inst|always5~9432 ;
wire \inst|always5~9433 ;
wire \inst|always5~9434 ;
wire \inst|always5~9435 ;
wire \inst|always5~9437 ;
wire \inst|always5~9455 ;
wire \inst|always5~9477 ;
wire \inst|always5~9478 ;
wire \inst|always5~9475 ;
wire \inst|always5~9479 ;
wire \inst|always5~9459 ;
wire \inst|always5~9469 ;
wire \inst|LessThan~4977 ;
wire \inst|always5~9470 ;
wire \inst|always5~9465 ;
wire \inst|always5~9466 ;
wire \inst|always5~9467 ;
wire \inst|always5~9468 ;
wire \inst|always5~9538 ;
wire \inst|always5~9471 ;
wire \inst|always5~9457 ;
wire \inst|always5~9458 ;
wire \inst|always5~9460 ;
wire \inst|always5~9461 ;
wire \inst|always5~9462 ;
wire \inst|always5~9463 ;
wire \inst|always5~9464 ;
wire \inst|always5~9472 ;
wire \inst|always5~9473 ;
wire \inst|always5~9474 ;
wire \inst|pixel[1]~557 ;
wire \inst|always5~9515 ;
wire \inst|always5~9516 ;
wire \inst|always5~9512 ;
wire \inst|always5~9511 ;
wire \inst|always5~9513 ;
wire \inst|LessThan~5000 ;
wire \inst|always5~9505 ;
wire \inst|always5~9506 ;
wire \inst|always5~9507 ;
wire \inst|always5~9508 ;
wire \inst|always5~9509 ;
wire \inst|always5~9510 ;
wire \inst|always5~9514 ;
wire \inst|always5~9517 ;
wire \inst|pixel[1]~559 ;
wire \inst|always5~9532 ;
wire \inst|always5~9520 ;
wire \inst|LessThan~4987 ;
wire \inst|LessThan~4988 ;
wire \inst|always5~9539 ;
wire \inst|LessThan~4989 ;
wire \inst|LessThan~4991 ;
wire \inst|always5~9523 ;
wire \inst|always5~9524 ;
wire \inst|always5~9525 ;
wire \inst|always5~9526 ;
wire \inst|always5~9527 ;
wire \inst|always5~9533 ;
wire \inst|LessThan~4992 ;
wire \inst|always5~9521 ;
wire \inst|always5~9522 ;
wire \inst|LessThan~4993 ;
wire \inst|always5~9528 ;
wire \inst|always5~9529 ;
wire \inst|always5~9530 ;
wire \inst|always5~9531 ;
wire \inst|always5~9535 ;
wire \inst|always5~9534 ;
wire \inst|always5~9536 ;
wire \inst|always5~9537 ;
wire \inst|pixel[1]~560 ;
wire \inst|pixel[0]~561 ;
wire \inst|pixel[0]~562 ;
wire \inst|pixel[0]~563 ;

wire [5:0] \inst4|altpll_component|pll_CLK_bus ;

assign \inst4|altpll_component|_clk0  = \inst4|altpll_component|pll_CLK_bus [0];
assign \inst4|altpll_component|_clk1  = \inst4|altpll_component|pll_CLK_bus [1];
assign \inst4|altpll_component|_clk2  = \inst4|altpll_component|pll_CLK_bus [2];
assign \inst4|altpll_component|_clk3  = \inst4|altpll_component|pll_CLK_bus [3];
assign \inst4|altpll_component|_clk4  = \inst4|altpll_component|pll_CLK_bus [4];
assign \inst4|altpll_component|_clk5  = \inst4|altpll_component|pll_CLK_bus [5];

// atom is at PIN_153
cyclone_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PLL_2
cyclone_pll \inst4|altpll_component|pll (
	.fbin(vcc),
	.ena(vcc),
	.clkswitch(gnd),
	.areset(gnd),
	.pfdena(vcc),
	.scanclk(gnd),
	.scanaclr(gnd),
	.scandata(vcc),
	.comparator(gnd),
	.inclk({gnd,\clk~combout }),
	.clkena({vcc,vcc,vcc,vcc,vcc,vcc}),
	.extclkena({vcc,vcc,vcc,vcc}),
	.activeclock(),
	.clkloss(),
	.locked(),
	.scandataout(),
	.enable0(),
	.enable1(),
	.clk(\inst4|altpll_component|pll_CLK_bus ),
	.extclk(),
	.clkbad());
// synopsys translate_off
defparam \inst4|altpll_component|pll .operation_mode = "normal";
defparam \inst4|altpll_component|pll .pll_type = "auto";
defparam \inst4|altpll_component|pll .qualify_conf_done = "off";
defparam \inst4|altpll_component|pll .valid_lock_multiplier = 1;
defparam \inst4|altpll_component|pll .invalid_lock_multiplier = 5;
defparam \inst4|altpll_component|pll .compensate_clock = "clk0";
defparam \inst4|altpll_component|pll .inclk0_input_frequency = 20000;
defparam \inst4|altpll_component|pll .inclk1_input_frequency = 20000;
defparam \inst4|altpll_component|pll .pfd_min = 5000;
defparam \inst4|altpll_component|pll .pfd_max = 66666;
defparam \inst4|altpll_component|pll .vco_min = 1000;
defparam \inst4|altpll_component|pll .vco_max = 2037;
defparam \inst4|altpll_component|pll .vco_center = 1250;
defparam \inst4|altpll_component|pll .pll_compensation_delay = 5369;
defparam \inst4|altpll_component|pll .skip_vco = "off";
defparam \inst4|altpll_component|pll .primary_clock = "inclk0";
defparam \inst4|altpll_component|pll .switch_over_on_lossclk = "off";
defparam \inst4|altpll_component|pll .switch_over_on_gated_lock = "off";
defparam \inst4|altpll_component|pll .enable_switch_over_counter = "off";
defparam \inst4|altpll_component|pll .gate_lock_signal = "no";
defparam \inst4|altpll_component|pll .gate_lock_counter = 0;
defparam \inst4|altpll_component|pll .switch_over_counter = 1;
defparam \inst4|altpll_component|pll .m = 16;
defparam \inst4|altpll_component|pll .n = 1;
defparam \inst4|altpll_component|pll .m2 = 1;
defparam \inst4|altpll_component|pll .n2 = 1;
defparam \inst4|altpll_component|pll .charge_pump_current = 40;
defparam \inst4|altpll_component|pll .loop_filter_c = 10;
defparam \inst4|altpll_component|pll .loop_filter_r = "1.021000";
defparam \inst4|altpll_component|pll .clk0_counter = "g1";
defparam \inst4|altpll_component|pll .l0_mode = "odd";
defparam \inst4|altpll_component|pll .l1_mode = "bypass";
defparam \inst4|altpll_component|pll .g0_mode = "bypass";
defparam \inst4|altpll_component|pll .g1_mode = "even";
defparam \inst4|altpll_component|pll .g2_mode = "bypass";
defparam \inst4|altpll_component|pll .g3_mode = "bypass";
defparam \inst4|altpll_component|pll .e0_mode = "bypass";
defparam \inst4|altpll_component|pll .e1_mode = "bypass";
defparam \inst4|altpll_component|pll .e2_mode = "bypass";
defparam \inst4|altpll_component|pll .e3_mode = "bypass";
defparam \inst4|altpll_component|pll .l0_high = 8;
defparam \inst4|altpll_component|pll .g1_high = 10;
defparam \inst4|altpll_component|pll .l0_low = 7;
defparam \inst4|altpll_component|pll .g1_low = 10;
defparam \inst4|altpll_component|pll .m_initial = 1;
defparam \inst4|altpll_component|pll .l0_initial = 1;
defparam \inst4|altpll_component|pll .g1_initial = 1;
defparam \inst4|altpll_component|pll .m_ph = 0;
defparam \inst4|altpll_component|pll .l0_ph = 0;
defparam \inst4|altpll_component|pll .l1_ph = 0;
defparam \inst4|altpll_component|pll .g0_ph = 0;
defparam \inst4|altpll_component|pll .g1_ph = 0;
defparam \inst4|altpll_component|pll .g2_ph = 0;
defparam \inst4|altpll_component|pll .g3_ph = 0;
defparam \inst4|altpll_component|pll .e0_ph = 0;
defparam \inst4|altpll_component|pll .e1_ph = 0;
defparam \inst4|altpll_component|pll .e2_ph = 0;
defparam \inst4|altpll_component|pll .e3_ph = 0;
defparam \inst4|altpll_component|pll .m_time_delay = 0;
defparam \inst4|altpll_component|pll .n_time_delay = 0;
defparam \inst4|altpll_component|pll .l0_time_delay = 0;
defparam \inst4|altpll_component|pll .l1_time_delay = 0;
defparam \inst4|altpll_component|pll .g0_time_delay = 0;
defparam \inst4|altpll_component|pll .g1_time_delay = 0;
defparam \inst4|altpll_component|pll .g2_time_delay = 0;
defparam \inst4|altpll_component|pll .g3_time_delay = 0;
defparam \inst4|altpll_component|pll .e0_time_delay = 0;
defparam \inst4|altpll_component|pll .e1_time_delay = 0;
defparam \inst4|altpll_component|pll .e2_time_delay = 0;
defparam \inst4|altpll_component|pll .e3_time_delay = 0;
defparam \inst4|altpll_component|pll .bandwidth_type = "auto";
defparam \inst4|altpll_component|pll .bandwidth = 1295546;
defparam \inst4|altpll_component|pll .spread_frequency = 0;
defparam \inst4|altpll_component|pll .down_spread = "0 %";
defparam \inst4|altpll_component|pll .clk0_multiply_by = 4;
defparam \inst4|altpll_component|pll .clk1_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk2_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk3_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk4_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk5_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk0_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk1_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk2_multiply_by = 1;