cam.vhd

用VHDL编写的程序

--A.5 cam.vhd
----------------------------------------------------------------------------
-- Title : Content Addressable Memory
-- Project :
----------------------------------------------------------------------------
-- File : cam.vhd
-- Author : Jevosnguan
-- Company :
-- Last update: 2005/11/18
-- Platform :
-- Reference : Philip Douglass, and Deepak George
----------------------------------------------------------------------------
--
-- **********************************************************************--
-- Title: Content Access Memory (CAM)
-- Description: This is the code for a Content Access Type of memory,
-- Adding Generics so that the width and depth can be changed. CAM
-- will match the contents of the TAG with the datain and if a match is
-- found HIT is made high and the appropriate data is outputed on the
-- dataout port.
-- ************************************************************************
----------------------------------------------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
--use work.types.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--use std.textio.all;
entity cam is
  generic (
	camWidthIn : natural := 8; -- width of cam memory tags
	camWidthOut: natural := 2; -- width of cam mem data
	camDepth : natural := 4 -- size of memory (num of tags and data)
    );
  port (
	clk : in std_ulogic; -- Clock
	datain : in std_ulogic_vector(camWidthOut-1 downto 0); -- data in
	data_out : out std_ulogic_vector(camWidthOut-1 downto 0); -- Data out
	full : out std_ulogic; -- Stack Full
	hit : out std_ulogic; -- Found Match
	rd_b : in std_ulogic; -- Read
	rst : in std_ulogic; -- Reset
	tagin : in std_ulogic_vector(camWidthIn-1 downto 0); -- Tag Data
	ctlTagIn : in std_ulogic_vector(camWidthIn-1 downto 0);--tag input from ctl
	wr_b : in std_ulogic -- Write
    );
end cam;
architecture behavioural of cam is
--Tags and data are stored in two arrays, where the data corresponding to a
--tag must live at the same location in the arrays
type tag_array is array (0 to camDepth-1 ) of std_ulogic_vector(camWidthIn-1 downto 0);
type data_array is array (0 to camDepth-1 ) of std_ulogic_vector(camWidthOut-1 downto 0);
signal count : integer range 0 to camDepth; --The number of elements stored in CAM
begin
main : process(rst, clk)
variable addr : natural; -- for loop counter
variable tag : tag_array;
variable data : data_array;
variable found : std_ulogic;
begin
  if (rst = '1') then
	count<= 0;
	full <= '0';
	hit <= '0';
	tag := (others => (others => '0'));
	data := (others => (others => '0'));
  elsif ( clk'event and clk='1') then
	-----------------------------------------------------------------------
	-- Stack Write Operation
	-----------------------------------------------------------------------
	if (wr_b = '1' and rd_b = '0') then
	  if ( count = camDepth ) then   --Do not add when cam is full
		full <= '1';
	  else
	    found := '0'; --Check to see if tag is already in table
	    for addr in 0 to camDepth-1 loop
	    if ctlTagIn = tag(conv_integer (addr)) then
		  data ( conv_integer (addr)) := datain; --Update data
		  found := '1'; --Found match
		end if;
	    end loop;
	    if found /= '1' then --If tag is not in table, add new
			tag (conv_integer (count)):= ctlTagIn;
			data(conv_integer (count)):= datain;
			count <= count +1;
		end if;
	  end if;
	---------------------------------------------------------------------------
	-- Stack CAM Read Operation
	---------------------------------------------------------------------------
	elsif (wr_b = '0' and rd_b = '1') then
	  found := '0';
	  for addr in 0 to camDepth-1 loop -- Check for data
	  if tagin = tag(conv_integer (addr)) then
	     data_out <= data ( conv_integer (addr));
	     found := '1'; --Found match
	  end if;
	  end loop;
	  hit <= found;
	end if;
  end if;
end process;

end behavioural;