8阶对称系数并行fir滤波器.v

8阶对称系数并行FIR滤波器(verilog)用作数字滤波

//8阶对称系数并行FIR滤波器

module fir(clk,rst,fir_in,fir_out);
parameter IDATA_WIDTH=12;
parameter PDATA_WIDTH=13;
parameter FIR_TAP=8;
parameter FIR_TAPHALF=4;
parameter COEFF_WIDTH=12;
parameter OUT_WIDTH=27;

parameter cof1=12'd41;
parameter cof2=12'd132;
parameter cof3=12'd341;
parameter cof4=12'd510;

input clk;
input rst;
input [IDATA_WIDTH-1:0] fir_in;
output [OUT_WIDTH-1:0] fir_out;

reg [OUT_WIDTH-1:0] fir_out;
reg [IDATA_WIDTH-1:0] fir_in_reg;
reg [PDATA_WIDTH-1:0] shift_buf[FIR_TAP-1:0]		//define 8 shift buffer

reg [PDATA_WIDTH-1:0] add07;
reg [PDATA_WIDTH-1:0] add16;
reg [PDATA_WIDTH-1:0] add25;
reg [PDATA_WIDTH-1:0] add34;

wire [PDATA_WIDTH+COEFF_WIDTH-1:0] mul1;
wire [PDATA_WIDTH+COEFF_WIDTH-1:0] mul2;
wire [PDATA_WIDTH+COEFF_WIDTH-1:0] mul3;
wire [PDATA_WIDTH+COEFF_WIDTH-1:0] mul4;

reg [PDATA_WIDTH+COEFF_WIDTH-1:0] mul1_reg;
reg [PDATA_WIDTH+COEFF_WIDTH-1:0] mul2_reg;
reg [PDATA_WIDTH+COEFF_WIDTH-1:0] mul3_reg;
reg [PDATA_WIDTH+COEFF_WIDTH-1:0] mul4_reg;

reg [PDATA_WIDTH+COEFF_WIDTH:0] add_mul12;
reg [PDATA_WIDTH+COEFF_WIDTH:0] add_mul34;
integer i,j;

always @(posedge clk or negedge rst) begin
	if(!rst)
		fir_in_reg<=12'h0;
	else
		fir_in_reg<=fir_in;
end

always @(posedge clk or negedge rst) begin
	if(!rst)
		for(i=0;i<=FIR_TAP-1;i=i+1)
			shift_buf[i]<=13'h0;
	else begin
		for(j=0;j<FIR_TAP-1;j=j+1)
			shift_buf[j+1]<=shift_buf[j];
		shift_buf[0]<={fir_in_reg[IDATA_WIDTH-1],fir_in_reg};		//sign expand
	end
end

always @(posedge clk or negedge rst) begin
	if(rst) begin
		add07<=13'h0;
		add16<=13'h0;
		add25<=13'h0;
		add34<=13'h0;
	end
	else begin
		add07<=shift_buf[0]+shift_buf[7];
		add16<=shift_buf[1]+shift_buf[6];
		add25<=shift_buf[2]+shift_buf[5];
		add34<=shift_buf[3]+shift_buf[4];
	end
end

mul12X13 mul1_ins(cof1,add07,mul1);
mul12X13 mul2_ins(cof2,add16,mul2);
mul12X13 mul3_ins(cof3,add25,mul3);
mul12X13 mul4_ins(cof4,add34,mul4);

always @(posedge clk or negedge rst) begin
	if(!rst) begin
		mul1_reg<=25'h0;
		mul2_reg<=25'h0;
		mul3_reg<=25'h0;
		mul4_reg<=25'h0;
	end
	else begin
		mul1_reg<=mul1;
		mul2_reg<=mul2;
		mul3_reg<=mul3;
		mul4_reg<=mul4;
	end
end

always @(posedge clk or negedge rst) begin
	if(!rst) begin
		add_mul12<=26'h0;
		add_mul34<=26'h0;
	end
	else begin
		add_mul12={mul1_reg[24],mul1_reg}+{mul2_reg[24],mul2_reg};
		add_mul34={mul3_reg[24],mul3_reg}+{mul4_reg[24],mul4_reg};
	end
end

always @(posedge clk or negedge rst) begin
	if(!rst)
		fir_out<=27'h0;
	else
		fir_out<={add_mul12[25],add_mul12}+{add_mul34[25],add_mul34};
end
endmodule