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📄 altsyncram_p3c1.tdf

📁 DE2开发版的默认程序
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		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 172032,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 176127,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 21504,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 22015,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a43 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 176128,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 180223,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 22016,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 22527,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a44 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 180224,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 184319,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 22528,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 23039,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a45 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 184320,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 188415,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 23040,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 23551,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a46 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 188416,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 192511,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 23552,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 24063,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a47 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 192512,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 196607,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 24064,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 24575,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a48 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 196608,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 200703,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 24576,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 25087,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a49 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 200704,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 204799,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 25088,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 25599,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a50 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 204800,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 208895,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 25600,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 26111,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a51 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 208896,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 212991,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 26112,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 26623,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a52 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "Img_DATA.hex",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 212992,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 217087,
			PORT_A_LOGICAL_RAM_DEPTH = 307200,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 8,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 26624,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 27135,
			PORT_B_LOGICAL_RAM_DEPTH = 38400,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE =
12345

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