altsyncram_p3c1.tdf
来自「DE2开发版的默认程序」· TDF 代码 · 共 1,805 行 · 第 1/5 页
TDF
1,805 行
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 81920,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 86015,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 10240,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 10751,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a21 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 86016,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 90111,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 10752,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 11263,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a22 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 90112,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 94207,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 11264,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 11775,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a23 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 94208,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 98303,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 11776,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 12287,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a24 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 98304,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 102399,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 12288,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 12799,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a25 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 102400,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 106495,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 12800,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 13311,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a26 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 106496,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 110591,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 13312,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 13823,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a27 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 110592,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 114687,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 13824,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 14335,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a28 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 114688,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 118783,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 14336,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 14847,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a29 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 118784,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 122879,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 14848,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 15359,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a30 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
INIT_FILE = "Img_DATA.hex",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_A_FIRST_ADDRESS = 122880,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 126975,
PORT_A_LOGICAL_RAM_DEPTH = 307200,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 9,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
PORT_B_FIRST_ADDRESS = 15360,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 15871,
PORT_B_LOGICAL_RAM_DEPTH = 38400,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a31 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
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