📄 hdb3.fit.rpt
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+----------------------------+-----------------------+
; C4s ; 7 / 8,840 ( < 1 % ) ;
; Direct links ; 5 / 11,506 ( < 1 % ) ;
; Global clocks ; 1 / 8 ( 12 % ) ;
; LAB clocks ; 2 / 156 ( 1 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 16 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 6 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 4.40) ; Number of LABs (Total = 5) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.20) ; Number of LABs (Total = 5) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 5 ;
; 2 Clock enables ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 4.80) ; Number of LABs (Total = 5) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 2.60) ; Number of LABs (Total = 5) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.60) ; Number of LABs (Total = 5) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Fri Jul 15 01:17:00 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off hdb3 -c hdb3
Info: Selected device EP1C3T144C8 for design "hdb3"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 4 pins of 4 total pins
Info: Pin pos_out not assigned to an exact location on the device
Info: Pin neg_out not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin data_in not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 1 input, 2 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 19 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 26 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 2.709 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y9; Fanout = 4; REG Node = 'CNT0[0]'
Info: 2: + IC(0.151 ns) + CELL(0.590 ns) = 0.741 ns; Loc. = LAB_X2_Y9; Fanout = 5; COMB Node = 'POS_OUT_TEMP~104'
Info: 3: + IC(0.075 ns) + CELL(0.590 ns) = 1.406 ns; Loc. = LAB_X2_Y9; Fanout = 1; COMB Node = 'B~1'
Info: 4: + IC(0.436 ns) + CELL(0.867 ns) = 2.709 ns; Loc. = LAB_X2_Y9; Fanout = 2; REG Node = 'B'
Info: Total cell delay = 2.047 ns ( 75.56 % )
Info: Total interconnect delay = 0.662 ns ( 24.44 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jul 15 01:17:11 2005
Info: Elapsed time: 00:00:11
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