hdb3decoder.map.eqn

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

--A1L7Q is NRZ~reg0
--operation mode is normal

A1L7Q_lut_out = SEQUENCE[3];
A1L7Q = DFFEAS(A1L7Q_lut_out, CLK, CLR, , , , , , );


--SEQUENCE[3] is SEQUENCE[3]
--operation mode is normal

SEQUENCE[3]_lut_out = SEQUENCE[2] & A1L71 # SEQUENCE[1] # SEQUENCE[0];
SEQUENCE[3] = DFFEAS(SEQUENCE[3]_lut_out, !CLK, CLR, , , , , , );


--SEQUENCE[2] is SEQUENCE[2]
--operation mode is normal

SEQUENCE[2]_lut_out = SEQUENCE[1];
SEQUENCE[2] = DFFEAS(SEQUENCE[2]_lut_out, !CLK, CLR, , , , , , );


--NEG_IN_TMP is NEG_IN_TMP
--operation mode is normal

NEG_IN_TMP_lut_out = NEG_IN;
NEG_IN_TMP = DFFEAS(NEG_IN_TMP_lut_out, CLK, CLR, , , , , , );


--POS_IN_TMP is POS_IN_TMP
--operation mode is normal

POS_IN_TMP_lut_out = POS_IN;
POS_IN_TMP = DFFEAS(POS_IN_TMP_lut_out, CLK, CLR, , , , , , );


--NEG_FLAG is NEG_FLAG
--operation mode is normal

NEG_FLAG_lut_out = NEG_IN_TMP & NEG_FLAG # !POS_IN_TMP # !NEG_IN_TMP & NEG_FLAG & !POS_IN_TMP;
NEG_FLAG = DFFEAS(NEG_FLAG_lut_out, !CLK, CLR, , , , , , );


--POS_FLAG is POS_FLAG
--operation mode is normal

POS_FLAG_lut_out = POS_IN_TMP & !NEG_IN_TMP;
POS_FLAG = DFFEAS(POS_FLAG_lut_out, !CLK, CLR, , A1L11, , , , );


--A1L71 is SEQUENCE~611
--operation mode is normal

A1L71 = NEG_IN_TMP & POS_IN_TMP # !NEG_FLAG # !NEG_IN_TMP & !POS_FLAG # !POS_IN_TMP;


--SEQUENCE[1] is SEQUENCE[1]
--operation mode is normal

SEQUENCE[1]_lut_out = SEQUENCE[0];
SEQUENCE[1] = DFFEAS(SEQUENCE[1]_lut_out, !CLK, CLR, , , , , , );


--SEQUENCE[0] is SEQUENCE[0]
--operation mode is normal

SEQUENCE[0]_lut_out = A1L81 # A1L91 & NEG_IN_TMP $ POS_IN_TMP;
SEQUENCE[0] = DFFEAS(SEQUENCE[0]_lut_out, !CLK, CLR, , , , , , );


--A1L11 is rtl~0
--operation mode is normal

A1L11 = NEG_IN_TMP $ POS_IN_TMP;


--A1L81 is SEQUENCE~613
--operation mode is normal

A1L81 = NEG_IN_TMP & !POS_IN_TMP & !NEG_FLAG # !NEG_IN_TMP & POS_IN_TMP & !POS_FLAG;


--A1L91 is SEQUENCE~614
--operation mode is normal

A1L91 = SEQUENCE[1] # SEQUENCE[0] # !SEQUENCE[3] & !SEQUENCE[2];


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CLR is CLR
--operation mode is input

CLR = INPUT();


--NEG_IN is NEG_IN
--operation mode is input

NEG_IN = INPUT();


--POS_IN is POS_IN
--operation mode is input

POS_IN = INPUT();


--NRZ is NRZ
--operation mode is output

NRZ = OUTPUT(A1L7Q);