a8251.fit.qmsg

8251的完整的功能的实现,可以进行编译,综合.

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRxC Global clock in PIN P2 " "Info: Automatically promoted signal \"nRxC\" to use Global clock in PIN P2" {  } { { "A8251.vhd" "" { Text "E:/UNZIPPED/8251_OSED/A8251.vhd" 46 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN P4 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN P4" {  } { { "A8251.vhd" "" { Text "E:/UNZIPPED/8251_OSED/A8251.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nTxC Global clock in PIN R2 " "Info: Automatically promoted signal \"nTxC\" to use Global clock in PIN R2" {  } { { "A8251.vhd" "" { Text "E:/UNZIPPED/8251_OSED/A8251.vhd" 45 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "DataLatch:i_DataSync\|LatchProc~2 Global clock " "Info: Automatically promoted signal \"DataLatch:i_DataSync\|LatchProc~2\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DataLatch:i_DataSync\|LatchProc~2" } } } } { "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" "" { Report "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" Compiler "A8251" "UNKNOWN" "V1" "E:/UNZIPPED/8251_OSED/db/A8251.quartus_db" { Floorplan "E:/UNZIPPED/8251_OSED/" "" "" { DataLatch:i_DataSync|LatchProc~2 } "NODE_NAME" } "" } } { "E:/UNZIPPED/8251_OSED/A8251.fld" "" { Floorplan "E:/UNZIPPED/8251_OSED/A8251.fld" "" "" { DataLatch:i_DataSync|LatchProc~2 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "proc:i_procintf\|proc_dec:I_proc_dec\|decode~51 Global clock " "Info: Automatically promoted some destinations of signal \"proc:i_procintf\|proc_dec:I_proc_dec\|decode~51\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Wr_Ext:i_Wr_Ext\|WriteExtProc~28 " "Info: Destination \"Wr_Ext:i_Wr_Ext\|WriteExtProc~28\" may be non-global or may not use global clock" {  } {  } 0}  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_dec:I_proc_dec\|decode~51" } } } } { "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" "" { Report "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" Compiler "A8251" "UNKNOWN" "V1" "E:/UNZIPPED/8251_OSED/db/A8251.quartus_db" { Floorplan "E:/UNZIPPED/8251_OSED/" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~51 } "NODE_NAME" } "" } } { "E:/UNZIPPED/8251_OSED/A8251.fld" "" { Floorplan "E:/UNZIPPED/8251_OSED/A8251.fld" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~51 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock in PIN R4 " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock in PIN R4" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_data_cnt:i_tx_data_cnt\|data_tc~40 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_data_cnt:i_tx_data_cnt\|data_tc~40\" may be non-global or may not use global clock" {  } { { "Tx_data_cnt.vhd" "" { Text "E:/UNZIPPED/8251_OSED/Tx_data_cnt.vhd" 55 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~4 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~4\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|reduce_nor~102 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|reduce_nor~102\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~3 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~3\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~1 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~1\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~232 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|equal~232\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1345 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1345\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|rxsync_proc2~0 " "Info: Destination \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|rxsync_proc2~0\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1350 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1350\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1352 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Select~1352\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "A8251.vhd" "" { Text "E:/UNZIPPED/8251_OSED/A8251.vhd" 37 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "tx_fifo:i_tx_fifo\|ff_wr_proc~21 Global clock " "Info: Automatically promoted signal \"tx_fifo:i_tx_fifo\|ff_wr_proc~21\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "tx_fifo:i_tx_fifo\|ff_wr_proc~21" } } } } { "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" "" { Report "E:/UNZIPPED/8251_OSED/db/A8251_cmp.qrpt" Compiler "A8251" "UNKNOWN" "V1" "E:/UNZIPPED/8251_OSED/db/A8251.quartus_db" { Floorplan "E:/UNZIPPED/8251_OSED/" "" "" { tx_fifo:i_tx_fifo|ff_wr_proc~21 } "NODE_NAME" } "" } } { "E:/UNZIPPED/8251_OSED/A8251.fld" "" { Floorplan "E:/UNZIPPED/8251_OSED/A8251.fld" "" "" { tx_fifo:i_tx_fifo|ff_wr_proc~21 } "NODE_NAME" } }  } 0}