m_bus.v

VERILOG五POSPHY LEVEL3电路描述

  if(~h_reset_n)
    begin
      fpga_csb       <=1'b1;
      pmc_3386_1_csb <=1'b1;
      pmc_3386_2_csb <=1'b1;
      pmc_5381_csb   <=1'b1;
      pmc_5382_csb   <=1'b1;
    end
  else if(~s_reset_n)
    begin
      fpga_csb       <=1'b1;
      pmc_3386_1_csb <=1'b1;
      pmc_3386_2_csb <=1'b1;
      pmc_5381_csb   <=1'b1;
      pmc_5382_csb   <=1'b1;  
    end
  else
    begin
      //fpga_csb       <=fpga_csb_tmp || fpga_csb_tmp_2d;      
      //pmc_3386_1_csb <=pmc_3386_1_csb_tmp || pmc_3386_1_csb_tmp_2d;
      //pmc_3386_2_csb <=pmc_3386_2_csb_tmp || pmc_3386_2_csb_tmp_2d;
      //pmc_5381_csb   <=pmc_5381_csb_tmp || pmc_5381_csb_tmp_2d;
      //pmc_5382_csb   <=pmc_5382_csb_tmp || pmc_5382_csb_tmp_2d;
      
      fpga_csb       <=mpc_csb || fpga_csb_tmp_d;
      pmc_3386_1_csb <=mpc_csb || pmc_3386_1_csb_tmp_d;
      pmc_3386_2_csb <=mpc_csb || pmc_3386_2_csb_tmp_d;
      pmc_5381_csb   <=mpc_csb || pmc_5381_csb_tmp_d;
      pmc_5382_csb   <=mpc_csb || pmc_5382_csb_tmp_d;  
    end
end

//fpga_csb_d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      fpga_csb_d       <=1'b1;
    end
  else if(~s_reset_n)
    begin
      fpga_csb_d       <=1'b1;      
    end
  else
    begin
      fpga_csb_d       <=fpga_csb;
    end
end

//rdb
//mpc_rdb_d,_2d,_3d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      mpc_rdb_d <=1'b1;
      mpc_rdb_2d<=1'b1;
      mpc_rdb_3d<=1'b1; 
    end
  else if(~s_reset_n)
    begin
      mpc_rdb_d <=1'b1;
      mpc_rdb_2d<=1'b1;
      mpc_rdb_3d<=1'b1;  
    end
  else
    begin
      mpc_rdb_d <=mpc_rdb;
      mpc_rdb_2d<=mpc_rdb_d;
      mpc_rdb_3d<=mpc_rdb_2d; 
    end
end

//pmc_rdb
//assign pmc_rdb = mpc_rdb_d || mpc_rdb_3d;

always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      pmc_rdb <=1'b1;      
    end
  else if(~s_reset_n)
    begin
      pmc_rdb <=1'b1;  
    end
  else
    begin
      //pmc_rdb <=mpc_rdb_d || mpc_rdb_3d;
      pmc_rdb <=mpc_rdb || mpc_rdb_2d;
    end
end

//wrb
//mpc_wrb_d,-2d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      mpc_wrb_d <=1'b1;
      mpc_wrb_2d<=1'b1;
    end
  else if(~s_reset_n)
    begin
      mpc_wrb_d <=1'b1;
      mpc_wrb_2d<=1'b1; 
    end
  else
    begin
      mpc_wrb_d <=mpc_wrb;
      mpc_wrb_2d<=mpc_wrb_d;
    end
end

//pmc_wrb
//assign pmc_wrb =mpc_wrb || mpc_wrb_2d;

always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      pmc_wrb <=1'b1;
    end
  else if(~s_reset_n)
    begin
      pmc_wrb <=1'b1;
    end
  else
    begin
      //pmc_wrb <=mpc_wrb || mpc_wrb_2d;
      pmc_wrb <=mpc_csb || mpc_wrb_d;
    end
end

//addr
//mpc_addr_d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      mpc_addr_d <=16'b0;
    end
  else if(~s_reset_n)
    begin
      mpc_addr_d <=16'b0;
    end
  else
    begin
      mpc_addr_d <=mpc_addr;
    end
end

//mpc_csb_d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      mpc_csb_d <=1'b1;
    end
  else if(~s_reset_n)
    begin
      mpc_csb_d <=1'b1;
    end
  else
    begin
      mpc_csb_d <=mpc_csb;
    end
end

//pmc_addr
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      pmc_addr[12:0]<=13'b0;
    end
  else if(~s_reset_n)
    begin
      pmc_addr[12:0]<=13'b0;
    end
  else if(~mpc_csb)
    begin
      pmc_addr[12:0]<=mpc_addr[12:0];
    end
  else if(~mpc_csb_d)
    begin
      pmc_addr[12:0]<=mpc_addr_d[12:0];
    end
  else
    begin
      pmc_addr[12:0]<=13'b0;
    end
end

//data
//rd_fpga_data_tmp
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rd_fpga_data_tmp[15:0]<=16'b0;
    end
  else if(~s_reset_n)
    begin
      rd_fpga_data_tmp[15:0]<=16'b0;
    end
  else if(~fpga_csb && ~pmc_rdb)
    begin
      case(pmc_addr[12:0])
        13'd0:rd_fpga_data_tmp[15:0]<=reset_sel[15:0];
        13'd1:rd_fpga_data_tmp[15:0]<=header_len_sel[15:0];
        13'd2:rd_fpga_data_tmp[15:0]<=crc_len_sel[15:0];
        //ge0_da_mac
        13'd3:rd_fpga_data_tmp[15:0]<=ge0_da_mac_0[15:0];
        13'd4:rd_fpga_data_tmp[15:0]<=ge0_da_mac_1[15:0];
        13'd5:rd_fpga_data_tmp[15:0]<=ge0_da_mac_2[15:0];
        //ge0_sa_mac
        13'd6:rd_fpga_data_tmp[15:0]<=ge0_sa_mac_0[15:0];
        13'd7:rd_fpga_data_tmp[15:0]<=ge0_sa_mac_1[15:0];
        13'd8:rd_fpga_data_tmp[15:0]<=ge0_sa_mac_2[15:0];
        //ge1_da_mac
        13'd9: rd_fpga_data_tmp[15:0]<=ge1_da_mac_0[15:0];
        13'd10:rd_fpga_data_tmp[15:0]<=ge1_da_mac_1[15:0];
        13'd11:rd_fpga_data_tmp[15:0]<=ge1_da_mac_2[15:0];
        //ge1_sa_mac
        13'd12:rd_fpga_data_tmp[15:0]<=ge1_sa_mac_0[15:0];        
        13'd13:rd_fpga_data_tmp[15:0]<=ge1_sa_mac_1[15:0];
        13'd14:rd_fpga_data_tmp[15:0]<=ge1_sa_mac_2[15:0];
        //ge2_da_mac
        13'd15:rd_fpga_data_tmp[15:0]<=ge2_da_mac_0[15:0];
        13'd16:rd_fpga_data_tmp[15:0]<=ge2_da_mac_1[15:0];
        13'd17:rd_fpga_data_tmp[15:0]<=ge2_da_mac_2[15:0];
        //ge2_sa_mac
        13'd18:rd_fpga_data_tmp[15:0]<=ge2_sa_mac_0[15:0];
        13'd19:rd_fpga_data_tmp[15:0]<=ge2_sa_mac_1[15:0];
        13'd20:rd_fpga_data_tmp[15:0]<=ge2_sa_mac_2[15:0];
        //ge3_da_mac
        13'd21:rd_fpga_data_tmp[15:0]<=ge3_da_mac_0[15:0];
        13'd22:rd_fpga_data_tmp[15:0]<=ge3_da_mac_1[15:0];
        13'd23:rd_fpga_data_tmp[15:0]<=ge3_da_mac_2[15:0];
        //ge3_sa_mac
        13'd24:rd_fpga_data_tmp[15:0]<=ge3_sa_mac_0[15:0];
        13'd25:rd_fpga_data_tmp[15:0]<=ge3_sa_mac_1[15:0];
        13'd26:rd_fpga_data_tmp[15:0]<=ge3_sa_mac_2[15:0];
        //lose_pkt_cnt
        13'd27:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch0[15:0];
        13'd28:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch1[15:0];
        13'd29:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch2[15:0];
        13'd30:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch3[15:0];
        13'd31:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch4[15:0];
        13'd32:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch5[15:0];
        13'd33:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch6[15:0];
        13'd34:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch7[15:0];
        13'd35:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch8[15:0];
        13'd36:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch9[15:0];
        13'd37:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch10[15:0];
        13'd38:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch11[15:0];
        13'd39:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch12[15:0];
        13'd40:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch13[15:0];
        13'd41:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch14[15:0];
        13'd42:rd_fpga_data_tmp[15:0]<=lose_pkt_cnt_ch15[15:0];
        default:rd_fpga_data_tmp[15:0]<=16'b0;
      endcase
    end
  else
    begin
      rd_fpga_data_tmp[15:0]<=16'b0;
    end
end

//reset_time_cnt
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      reset_time_cnt[7:0]<=8'd0;
    end
  else if(~s_reset_n)
    begin
      reset_time_cnt[7:0]<=8'd0;
    end
  else if(reset_sel[0]||reset_sel[1]||reset_sel[2]||reset_sel[3]||reset_sel[4]||reset_sel[5])
    begin
      reset_time_cnt[7:0]<=reset_time_cnt[7:0] + 8'd1;
    end
  else
    begin
      reset_time_cnt[7:0]<=8'd0;
    end
end

//write fpga reg
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      reset_sel[15:0]     <=16'b0000_0000_0000_00000;
      header_len_sel[15:0]<=16'b0000_0000_0000_00000;
      crc_len_sel[15:0]   <=16'b0000_0000_0000_00001;
      
      //ge0_da_mac
      ge0_da_mac_0[15:0] <=16'h2211;//16'b0000_0000_0000_00000;
      ge0_da_mac_1[15:0] <=16'h4433;//16'b0000_0000_0000_00000;
      ge0_da_mac_2[15:0] <=16'h6655;//16'b0000_0000_0000_00000;
      //ge0_sa_mac
      ge0_sa_mac_0[15:0] <=16'h8899;//16'b0000_0000_0000_00000;
      ge0_sa_mac_1[15:0] <=16'h6677;//16'b0000_0000_0000_00000;
      ge0_sa_mac_2[15:0] <=16'h4455;//16'b0000_0000_0000_00000;
      //ge1_da_mac
      ge1_da_mac_0[15:0]<=16'hbbaa;//16'b0000_0000_0000_00000;
      ge1_da_mac_1[15:0]<=16'hddcc;//16'b0000_0000_0000_00000;
      ge1_da_mac_2[15:0]<=16'hffee;//16'b0000_0000_0000_00000;
      //ge1_sa_mac                 //
      ge1_sa_mac_0[15:0]<=16'heeff;//16'b0000_0000_0000_00000;        
      ge1_sa_mac_1[15:0]<=16'hccdd;//16'b0000_0000_0000_00000;
      ge1_sa_mac_2[15:0]<=16'haabb;//16'b0000_0000_0000_00000;
      //ge2_da_mac
      ge2_da_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge2_da_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge2_da_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge2_sa_mac
      ge2_sa_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge2_sa_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge2_sa_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge3_da_mac
      ge3_da_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge3_da_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge3_da_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge3_sa_mac
      ge3_sa_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge3_sa_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge3_sa_mac_2[15:0]<=16'b0000_0000_0000_00000;
    end
  else if(~s_reset_n)
    begin
      reset_sel[15:0]     <=16'b0000_0000_0000_00000;
      header_len_sel[15:0]<=16'b0000_0000_0000_00000;
      crc_len_sel[15:0]   <=16'b0000_0000_0000_00001;
      
      //ge0_da_mac
      ge0_da_mac_0[15:0] <=16'b0000_0000_0000_00000;
      ge0_da_mac_1[15:0] <=16'b0000_0000_0000_00000;
      ge0_da_mac_2[15:0] <=16'b0000_0000_0000_00000;
      //ge0_sa_mac
      ge0_sa_mac_0[15:0] <=16'b0000_0000_0000_00000;
      ge0_sa_mac_1[15:0] <=16'b0000_0000_0000_00000;
      ge0_sa_mac_2[15:0] <=16'b0000_0000_0000_00000;
      //ge1_da_mac
      ge1_da_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge1_da_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge1_da_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge1_sa_mac
      ge1_sa_mac_0[15:0]<=16'b0000_0000_0000_00000;        
      ge1_sa_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge1_sa_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge2_da_mac
      ge2_da_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge2_da_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge2_da_mac_2[15:0]<=16'b0000_0000_0000_00000;
      //ge2_sa_mac
      ge2_sa_mac_0[15:0]<=16'b0000_0000_0000_00000;
      ge2_sa_mac_1[15:0]<=16'b0000_0000_0000_00000;
      ge2_sa_mac_2[15:0]<=16'b0000_0000_0000_00000;