rx_pkt_ram_pro.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : rx_pkt_ram_pro.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pmc5382_rx_pl3.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module rx_pkt_ram_pro(
                      //system signals
                      h_reset_n,
                      s_reset_n,
                      sys_clk_100m,
                      
                      //signals
                      wren_sop_tmp,
                      wren_eop_tmp,
                      wren_err_tmp,
                      wren_mod_tmp,
                      wren_data_tmp,
                      wren_val_tmp,
                      
                                                                                                                                                                                                                             
                      //signals to pmc3386_tx_pl3 block 
                      ch_fifo_aval,
                                                   
                      ch_fifo_rden,
                      
                      //ch
                      ch_fifo_data,
                      ch_fifo_sop,
                      ch_fifo_eop,
                      ch_fifo_mod,
                      ch_fifo_err, 
                      ch_fifo_par,
                      
                                                                    
                      ge_da_mac,
                      ge_sa_mac,
                      
                      //
                      lose_pkt_cnt,                                                                                          
                      //test signals
                      test_sel,
                      test_point                 
                      );
                       
                       
//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;

//signals
input wren_sop_tmp;
input wren_eop_tmp;
input wren_err_tmp;
input [1:0]wren_mod_tmp;
input [31:0]wren_data_tmp; 
input wren_val_tmp;

                                                                                                                                                                                                       
//signals to pmc3386_tx_pl3 block 
output ch_fifo_aval;
                            
input ch_fifo_rden;

//ch
output [31:0]ch_fifo_data;
output       ch_fifo_sop;
output       ch_fifo_eop;
output [1:0] ch_fifo_mod;
output       ch_fifo_err; 
output       ch_fifo_par;

                                              
input [47:0]ge_da_mac;
input [47:0]ge_sa_mac;
 
output [15:0]lose_pkt_cnt;                                                                                         
//test signals
input [7:0]test_sel;
output [31:0]test_point;                 

///////////////////////////////////////////////
reg ch_fifo_aval;                       

wire [31:0]ch_fifo_data;
wire       ch_fifo_sop;
wire       ch_fifo_eop;
wire [1:0] ch_fifo_mod;
wire       ch_fifo_err; 
wire       ch_fifo_par;

reg [15:0]lose_pkt_cnt;

wire  [31:0]test_point; 
/////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////

reg wren_sop;    
reg wren_eop;    
reg wren_err;   
reg wren_par;   
reg [1:0]wren_mod;        
reg [31:0]wren_data;

wire wr_ram_en;     
wire [35:0]wr_ram1_dq;
wire [1:0]wr_ram2_dq;

reg wr_pkt_unfinished_tmp;
reg [7:0]rcv_pkt_cnt;

reg wren_eop_tmp_d;
reg wren_eop_tmp_2d;
reg wren_eop_tmp_3d;

reg [1:0]wren_mod_tmp_d;
reg [1:0]wren_mod_tmp_2d;
reg [1:0]wren_mod_tmp_3d;

reg wren_err_tmp_d;
reg wren_err_tmp_2d;
reg wren_err_tmp_3d;

reg wren_sop_d;
reg wren_sop_2d;
reg wren_sop_3d;

reg [31:0]wren_data_tmp_d;
reg [31:0]wren_data_tmp_2d;
reg [31:0]wren_data_tmp_3d;

reg wren_sop_tmp_d;
reg wren_sop_tmp_2d;
reg wren_sop_tmp_3d;
 
reg wren_val_tmp_d;
reg wren_val_tmp_2d;
reg wren_val_tmp_3d;
reg wren_val_tmp_4d;

reg [9:0]packet_start_addx;
reg [9:0]wr_ram_addx;
reg rx_pkt_ram_full;
reg rx_pkt_ram_full_tmp;

reg ch_fifo_rden_d;
reg ch_fifo_rden_2d;

reg [9:0]rd_ram_addx; 

wire [35:0]rd_ram1_dq;
wire  [1:0]rd_ram2_dq;

reg ch_fifo_eop_d,ch_fifo_eop_2d;

///////////////////////////////////////////////////////////////////////////////////
assign test_point = 32'b0;
///////////////////////////////////////////////////////////////////////////////////
//-xd
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_eop_tmp_d  <=1'b0;
      wren_eop_tmp_2d <=1'b0;
      wren_eop_tmp_3d <=1'b0;
                      
      wren_mod_tmp_d  <=2'b0;
      wren_mod_tmp_2d <=2'b0;
      wren_mod_tmp_3d <=2'b0;
                      
      wren_err_tmp_d  <=1'b0;
      wren_err_tmp_2d <=1'b0;
      wren_err_tmp_3d <=1'b0;
                      
      wren_sop_d      <=1'b0;
      wren_sop_2d     <=1'b0;
      wren_sop_3d     <=1'b0;
                      
      //wren_data_tmp_d <=32'b0;
      //wren_data_tmp_2d<=32'b0;
      //wren_data_tmp_3d<=32'b0;
                      
      wren_sop_tmp_d  <=1'b0;
      wren_sop_tmp_2d <=1'b0;
      wren_sop_tmp_3d <=1'b0;
                      
      wren_val_tmp_d  <=1'b0;
      wren_val_tmp_2d <=1'b0;
      wren_val_tmp_3d <=1'b0;
      wren_val_tmp_4d <=1'b0;
      
      ch_fifo_rden_d <=1'b0;
      ch_fifo_rden_2d<=1'b0; 
      
      ch_fifo_eop_d  <=1'b0; 
      ch_fifo_eop_2d <=1'b0;  
    end
  else if(~s_reset_n)
    begin
       wren_eop_tmp_d  <=1'b0;
      wren_eop_tmp_2d <=1'b0;
      wren_eop_tmp_3d <=1'b0;
                      
      wren_mod_tmp_d  <=2'b0;
      wren_mod_tmp_2d <=2'b0;
      wren_mod_tmp_3d <=2'b0;
                      
      wren_err_tmp_d  <=1'b0;
      wren_err_tmp_2d <=1'b0;
      wren_err_tmp_3d <=1'b0;
                      
      wren_sop_d      <=1'b0;
      wren_sop_2d     <=1'b0;
      wren_sop_3d     <=1'b0;
                      
      //wren_data_tmp_d <=32'b0;
      //wren_data_tmp_2d<=32'b0;
      //wren_data_tmp_3d<=32'b0;
                      
      wren_sop_tmp_d  <=1'b0;
      wren_sop_tmp_2d <=1'b0;
      wren_sop_tmp_3d <=1'b0;
                      
      wren_val_tmp_d  <=1'b0;
      wren_val_tmp_2d <=1'b0;
      wren_val_tmp_3d <=1'b0;
      wren_val_tmp_4d <=1'b0; 
      
      ch_fifo_rden_d <=1'b0;
      ch_fifo_rden_2d<=1'b0;
      
      ch_fifo_eop_d  <=1'b0; 
      ch_fifo_eop_2d <=1'b0;  
    end
  else
    begin
      wren_eop_tmp_d  <=wren_eop_tmp;
      wren_eop_tmp_2d <=wren_eop_tmp_d ;
      wren_eop_tmp_3d <=wren_eop_tmp_2d;
                      
      wren_mod_tmp_d  <=wren_mod_tmp;
      wren_mod_tmp_2d <=wren_mod_tmp_d ;
      wren_mod_tmp_3d <=wren_mod_tmp_2d;
                      
      wren_err_tmp_d  <=wren_err_tmp;
      wren_err_tmp_2d <=wren_err_tmp_d ;
      wren_err_tmp_3d <=wren_err_tmp_2d;
                      
      wren_sop_d      <=wren_sop;
      wren_sop_2d     <=wren_sop_d ;
      wren_sop_3d     <=wren_sop_2d;
                      
      //wren_data_tmp_d <=wren_data_tmp;
      //wren_data_tmp_2d<=wren_data_tmp_d ;
      //wren_data_tmp_3d<=wren_data_tmp_2d;
                      
      wren_sop_tmp_d  <=wren_sop_tmp;
      wren_sop_tmp_2d <=wren_sop_tmp_d ;
      wren_sop_tmp_3d <=wren_sop_tmp_2d;
                      
      wren_val_tmp_d  <=wren_val_tmp;
      wren_val_tmp_2d <=wren_val_tmp_d ;
      wren_val_tmp_3d <=wren_val_tmp_2d;
      wren_val_tmp_4d <=wren_val_tmp_3d; 
      
      ch_fifo_rden_d <=ch_fifo_rden;
      ch_fifo_rden_2d<=ch_fifo_rden_d;
      
      ch_fifo_eop_d  <=ch_fifo_eop; 
      ch_fifo_eop_2d <=ch_fifo_eop_d; 
    end
end

always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_data_tmp_d <=32'b0;         
    end
  else if(~s_reset_n)
    begin
      wren_data_tmp_d <=32'b0;        
    end
  else if(wren_val_tmp)   
    begin
      wren_data_tmp_d <=wren_data_tmp;      
    end
  else
    begin
      wren_data_tmp_d <=wren_data_tmp_d;      
    end
end

always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_data_tmp_2d <=32'b0;
      wren_data_tmp_3d <=32'b0;         
    end
  else if(~s_reset_n)
    begin
      wren_data_tmp_2d <=32'b0;
      wren_data_tmp_3d <=32'b0;         
    end
  else
    begin
      wren_data_tmp_2d <=wren_data_tmp_d;
      wren_data_tmp_3d <=wren_data_tmp_2d;      
    end
end

//wren_sop
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
       wren_sop  <=1'b0;     
    end
  else if(~s_reset_n)
    begin
       wren_sop  <=1'b0;   
    end
  else
    begin
       wren_sop  <=wren_sop_tmp; 
    end
end

//wren_eop, wren_err, wren_mod
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      wren_eop <=1'b0;
      wren_err <=1'b0;
      wren_mod <=2'b0;  
    end
  else if(~s_reset_n)
    begin
      wren_eop <=1'b0;