pmc3386_tx_pl3.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : pmc3386_tx_pl3.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pmc5382_to_pmc3386_pl3.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module pmc3386_tx_pl3(
                       //system signals
                       h_reset_n,
                       s_reset_n,
                       sys_clk_100m,
                                             
                       //signals from pmc5382 block
                       pmc3386_tenb,
                       pmc3386_tsx,
                       pmc3386_tadr, 
                       pmc3386_ptpa,
                       pmc3386_stpa,
                       pmc3386_dtpa,                      
                       
                       
                       pmc3386_tdat,                      
                       pmc3386_tsop,
                       pmc3386_teop,
                       pmc3386_tmod,
                       pmc3386_terr,
                       pmc3386_tprty,
                                                                                                                                                                                                                              
                       //signals to pmc3386_tx_pl3 block 
                       ch0_fifo_aval,
                       ch1_fifo_aval,
                       ch2_fifo_aval,
                       ch3_fifo_aval,
                       ch4_fifo_aval,
                       ch5_fifo_aval,
                       ch6_fifo_aval,
                       ch7_fifo_aval,
                                              
                       ch0_fifo_rden,
                       ch1_fifo_rden,
                       ch2_fifo_rden,
                       ch3_fifo_rden,
                       ch4_fifo_rden,
                       ch5_fifo_rden,
                       ch6_fifo_rden,
                       ch7_fifo_rden,
                       
                       //ch0
                       ch0_fifo_data,
                       ch0_fifo_sop,
                       ch0_fifo_eop,
                       ch0_fifo_mod,
                       ch0_fifo_err, 
                       ch0_fifo_par,
                       //ch1
                       ch1_fifo_data,
                       ch1_fifo_sop,
                       ch1_fifo_eop,
                       ch1_fifo_mod,
                       ch1_fifo_err, 
                       ch1_fifo_par,
                       //ch2
                       ch2_fifo_data,
                       ch2_fifo_sop,
                       ch2_fifo_eop,
                       ch2_fifo_mod,
                       ch2_fifo_err, 
                       ch2_fifo_par,
                       //ch3
                       ch3_fifo_data,
                       ch3_fifo_sop,
                       ch3_fifo_eop,
                       ch3_fifo_mod,
                       ch3_fifo_err, 
                       ch3_fifo_par,
                       //ch4
                       ch4_fifo_data,
                       ch4_fifo_sop,
                       ch4_fifo_eop,
                       ch4_fifo_mod,
                       ch4_fifo_err, 
                       ch4_fifo_par,
                       //ch5
                       ch5_fifo_data,
                       ch5_fifo_sop,
                       ch5_fifo_eop,
                       ch5_fifo_mod,
                       ch5_fifo_err, 
                       ch5_fifo_par,
                       //ch6
                       ch6_fifo_data,
                       ch6_fifo_sop,
                       ch6_fifo_eop,
                       ch6_fifo_mod,
                       ch6_fifo_err, 
                       ch6_fifo_par,
                       //ch7
                       ch7_fifo_data,
                       ch7_fifo_sop,
                       ch7_fifo_eop,
                       ch7_fifo_mod,
                       ch7_fifo_err, 
                       ch7_fifo_par,                       
                                              
                       //test signals
                       test_sel,
                       test_point                 
                       );
                       
                       
//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;
                      
//signals to pmc3386 block
output pmc3386_tenb;
output pmc3386_tsx;
output pmc3386_tadr; 
input  pmc3386_ptpa;
input  pmc3386_stpa;
input  [1:0]pmc3386_dtpa;                      

output [31:0]pmc3386_tdat;                      
output       pmc3386_tsop;
output       pmc3386_teop;
output  [1:0]pmc3386_tmod;
output       pmc3386_terr;
output       pmc3386_tprty;
                                                                                                                                                                                                       
//signals from pmc5382_rx_pl3 block 
input ch0_fifo_aval;
input ch1_fifo_aval;
input ch2_fifo_aval;
input ch3_fifo_aval;
input ch4_fifo_aval;
input ch5_fifo_aval;
input ch6_fifo_aval;
input ch7_fifo_aval;

//signals to pmc5382_rx_pl3 block 
output ch0_fifo_rden;
output ch1_fifo_rden;
output ch2_fifo_rden;
output ch3_fifo_rden;
output ch4_fifo_rden;
output ch5_fifo_rden;
output ch6_fifo_rden;
output ch7_fifo_rden;

//ch0
input [31:0]ch0_fifo_data;
input       ch0_fifo_sop;
input       ch0_fifo_eop;
input  [1:0]ch0_fifo_mod;
input       ch0_fifo_err;
input       ch0_fifo_par; 
//ch1
input [31:0]ch1_fifo_data;
input       ch1_fifo_sop;
input       ch1_fifo_eop;
input  [1:0]ch1_fifo_mod;
input       ch1_fifo_err; 
input       ch1_fifo_par;
//ch2
input [31:0]ch2_fifo_data;
input       ch2_fifo_sop;
input       ch2_fifo_eop;
input  [1:0]ch2_fifo_mod;
input       ch2_fifo_err; 
input       ch2_fifo_par;
//ch3
input [31:0]ch3_fifo_data;
input       ch3_fifo_sop;
input       ch3_fifo_eop;
input  [1:0]ch3_fifo_mod;
input       ch3_fifo_err; 
input       ch3_fifo_par;
//ch4
input [31:0]ch4_fifo_data;
input       ch4_fifo_sop;
input       ch4_fifo_eop;
input  [1:0]ch4_fifo_mod;
input       ch4_fifo_err; 
input       ch4_fifo_par;
//ch5
input [31:0]ch5_fifo_data;
input       ch5_fifo_sop;
input       ch5_fifo_eop;
input  [1:0]ch5_fifo_mod;
input       ch5_fifo_err; 
input       ch5_fifo_par;
//ch6
input [31:0]ch6_fifo_data;
input       ch6_fifo_sop;
input       ch6_fifo_eop;
input  [1:0]ch6_fifo_mod;
input       ch6_fifo_err; 
input       ch6_fifo_par;
//ch7
input [31:0]ch7_fifo_data;
input       ch7_fifo_sop;
input       ch7_fifo_eop;
input  [1:0]ch7_fifo_mod;
input       ch7_fifo_err; 
input       ch7_fifo_par;
                                                                                                       
//test signals
input   [7:0]test_sel;
output [31:0]test_point;
/////////////////////////////////////////////////////////////////////////////////////////////
reg ch0_fifo_rden;
reg ch1_fifo_rden;
reg ch2_fifo_rden;
reg ch3_fifo_rden;
reg ch4_fifo_rden;
reg ch5_fifo_rden;
reg ch6_fifo_rden;
reg ch7_fifo_rden;

wire pmc3386_tadr;

wire pmc3386_tprty;
wire pmc3386_tprty_tmp;

reg [31:0]test_point;

/////////////////////////
//internal reg
//for b1 
reg ch0_pkt_unfinished;
reg ch1_pkt_unfinished; 
reg ch2_pkt_unfinished;  
reg ch3_pkt_unfinished;  

//reg ch0_fifo_rden_tmp;
//reg ch1_fifo_rden_tmp;
//reg ch2_fifo_rden_tmp;
//reg ch3_fifo_rden_tmp; 
      
reg [1:0]ch_id_for_b1;

reg ch0_fifo_rden_d;
reg ch1_fifo_rden_d;
reg ch2_fifo_rden_d;
reg ch3_fifo_rden_d;

reg ch0_fifo_rden_2d;
reg ch1_fifo_rden_2d;
reg ch2_fifo_rden_2d;
reg ch3_fifo_rden_2d;

wire      b1_dav; 
reg       b1_ena;
reg [31:0]b1_dat;
reg       b1_sop;
reg       b1_eop;
reg       b1_err;
reg       b1_par;
reg  [1:0]b1_mty;

//for b2
reg ch4_pkt_unfinished;
reg ch5_pkt_unfinished; 
reg ch6_pkt_unfinished;  
reg ch7_pkt_unfinished;  

//reg ch4_fifo_rden_tmp;
//reg ch5_fifo_rden_tmp;
//reg ch6_fifo_rden_tmp;
//reg ch7_fifo_rden_tmp; 
      
reg [1:0]ch_id_for_b2;

reg ch4_fifo_rden_d;
reg ch5_fifo_rden_d;
reg ch6_fifo_rden_d;
reg ch7_fifo_rden_d;

reg ch4_fifo_rden_2d;
reg ch5_fifo_rden_2d;
reg ch6_fifo_rden_2d;
reg ch7_fifo_rden_2d;

wire      b2_dav;	     
reg       b2_ena;
reg [31:0]b2_dat;
reg       b2_sop;
reg       b2_eop;
reg       b2_err;
reg       b2_par;
reg  [1:0]b2_mty;

reg      b1_dav_d;
reg      b2_dav_d;
///////////////////////////////////////////////////////////////////////////////////
//test point assignment
always @(*)
begin
  if(h_reset_n)
    begin
      test_point[31:0]<=32'b0;
    end
  else if(s_reset_n)
    begin
      test_point[31:0]<=32'b0;
    end
  else
    case(test_sel[3:0])
      4'b0000: test_point[31:0]<={pmc3386_tdat[20:0],pmc3386_tmod[1:0],pmc3386_tprty,pmc3386_terr,pmc3386_teop,pmc3386_tsop,pmc3386_dtpa[1:0],pmc3386_tsx,pmc3386_tenb,sys_clk_100m};
      4'b0001: test_point[31:0]<=32'b0;
      4'b0010: test_point[31:0]<=32'b0;      
      4'b0011: test_point[31:0]<=32'b0;
      4'b0100: test_point[31:0]<=32'b0;
      4'b0101: test_point[31:0]<=32'b0;
      4'b0110: test_point[31:0]<=32'b0;
      4'b0111: test_point[31:0]<=32'b0;
      4'b1000: test_point[31:0]<=32'b0;
      4'b1001: test_point[31:0]<=32'b0;
      4'b1010: test_point[31:0]<=32'b0;
      4'b1011: test_point[31:0]<=32'b0;
      4'b1100: test_point[31:0]<=32'b0;
      4'b1101: test_point[31:0]<=32'b0;
      4'b1110: test_point[31:0]<=32'b0;
      4'b1111: test_point[31:0]<=32'b0;
      default: ;
    endcase
end 
////////////////////////////////////////////////////////


assign pmc3386_tadr = 1'b0;

assign pmc3386_tprty = 1'b0;
//*****************************************************************************//
//for b1
//*****************************************************************************//
//ch0_pkt_unfinished
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      ch0_pkt_unfinished <=1'b0;    
    end
  else if(~s_reset_n)
    begin
      ch0_pkt_unfinished <=1'b0;
    end
  else if(ch0_fifo_sop && ch0_fifo_eop)
    begin
      ch0_pkt_unfinished <=1'b0;
    end
  else if(ch0_fifo_sop)
    begin
      ch0_pkt_unfinished <=1'b1;
    end
  else if(ch0_fifo_eop)
    begin
      ch0_pkt_unfinished <=1'b0;
    end
  else
    begin
      ch0_pkt_unfinished <=ch0_pkt_unfinished;
    end
end

//ch1_pkt_unfinished
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      ch1_pkt_unfinished <=1'b0;    
    end
  else if(~s_reset_n)
    begin
      ch1_pkt_unfinished <=1'b0;
    end
  else if(ch1_fifo_sop && ch1_fifo_eop)
    begin
      ch1_pkt_unfinished <=1'b0;
    end
  else if(ch1_fifo_sop)
    begin
      ch1_pkt_unfinished <=1'b1;
    end  
  else if(ch1_fifo_eop)
    begin
      ch1_pkt_unfinished <=1'b0;
    end
  else
    begin
      ch1_pkt_unfinished <=ch1_pkt_unfinished;
    end
end

//ch2_pkt_unfinished
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      ch2_pkt_unfinished <=1'b0;    
    end
  else if(~s_reset_n)
    begin
      ch2_pkt_unfinished <=1'b0;
    end
  else if(ch2_fifo_sop && ch2_fifo_eop)
    begin
      ch2_pkt_unfinished <=1'b0;
    end