link_phy_pl3.v

VERILOG五POSPHY LEVEL3电路描述

              if(~empty1&&a_dtpa[1])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd21;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
              end
        6'd21: begin
              if(~empty1&&a_dtpa[1])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd22;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
              end
        6'd22,
        6'd23,
        6'd24,
        6'd25,
        6'd26,
        6'd27,
        6'd28,
        6'd29,
        6'd30,
        6'd31,
        6'd32,
        6'd33,
        6'd34,
        6'd35,
        6'd36:  begin
              if(~empty1&&a_dtpa[1]&&~eop1)
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b1;
                  state[5:0]<=state[5:0] + 6'd1;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
              end
        6'd37: begin
              if(~empty1&&a_dtpa[1])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b1;
                  state[5:0]<=6'd0;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
              end
        default: begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
      endcase  
    end
end


//fifo output 0
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rden_fifo_valid0<=1'b0;
      rden_fifo_sop0<=1'b0;
      rden_fifo_eop0<=1'b0;
      rden_fifo_err0<=1'b0;
      rden_fifo_mod0[1:0]<=2'b0;
      rden_fifo_data0[31:0]<=32'b0;
    end
  else if(~s_reset_n)
    begin
      rden_fifo_valid0<=1'b0;
      rden_fifo_sop0<=1'b0;
      rden_fifo_eop0<=1'b0;
      rden_fifo_err0<=1'b0;
      rden_fifo_mod0[1:0]<=2'b0;
      rden_fifo_data0[31:0]<=32'b0;
    end
  else if(rdreq0_d)
    begin
      rden_fifo_valid0<=1'b1;
      rden_fifo_sop0<=q0[36];
      rden_fifo_eop0<=q0[35];
      rden_fifo_err0<=q0[34];
      rden_fifo_mod0[1:0]<=q0[33:32];
      rden_fifo_data0[31:0]<=q0[31:0]; 
    end
  else
    begin
      rden_fifo_valid0<=1'b0;
      rden_fifo_sop0<=1'b0;
      rden_fifo_eop0<=1'b0;
      rden_fifo_err0<=1'b0;
      rden_fifo_mod0[1:0]<=2'b0;
      rden_fifo_data0[31:0]<=32'b0;      
    end
end 



//fifo output 1
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rden_fifo_valid1<=1'b0;
      rden_fifo_sop1<=1'b0;
      rden_fifo_eop1<=1'b0;
      rden_fifo_err1<=1'b0;
      rden_fifo_mod1[1:0]<=2'b0;
      rden_fifo_data1[31:0]<=32'b0;
    end
  else if(~s_reset_n)
    begin
      rden_fifo_valid1<=1'b0;
      rden_fifo_sop1<=1'b0;
      rden_fifo_eop1<=1'b0;
      rden_fifo_err1<=1'b0;
      rden_fifo_mod1[1:0]<=2'b0;
      rden_fifo_data1[31:0]<=32'b0;
    end
  else if(rdreq1_d)
    begin
      rden_fifo_valid1<=1'b1;
      rden_fifo_sop1<=q1[36];
      rden_fifo_eop1<=q1[35];
      rden_fifo_err1<=q1[34];
      rden_fifo_mod1[1:0]<=q1[33:32];
      rden_fifo_data1[31:0]<=q1[31:0]; 
    end
  else
    begin
      rden_fifo_valid1<=1'b0;
      rden_fifo_sop1<=1'b0;
      rden_fifo_eop1<=1'b0;
      rden_fifo_err1<=1'b0;
      rden_fifo_mod1[1:0]<=2'b0;
      rden_fifo_data1[31:0]<=32'b0;      
    end
end 


//-d
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rdreq0_d <=1'b0;
      rdreq1_d <=1'b0;
      
      rden_fifo_valid0_d<=1'b0;
      rden_fifo_sop0_d<=1'b0;
      rden_fifo_eop0_d<=1'b0;
      rden_fifo_err0_d<=1'b0;
      rden_fifo_mod0_d[1:0]<=2'b0;
      rden_fifo_data0_d[31:0]<=32'b0;    
      
      rden_fifo_valid1_d<=1'b0;
      rden_fifo_sop1_d<=1'b0;
      rden_fifo_eop1_d<=1'b0;
      rden_fifo_err1_d<=1'b0;
      rden_fifo_mod1_d[1:0]<=2'b0;
      rden_fifo_data1_d[31:0]<=32'b0;
    end
  else if(~s_reset_n)
    begin
      rdreq0_d <=1'b0;
      rdreq1_d <=1'b0;
    
      rden_fifo_valid0_d<=1'b0;
      rden_fifo_sop0_d<=1'b0;
      rden_fifo_eop0_d<=1'b0;
      rden_fifo_err0_d<=1'b0;
      rden_fifo_mod0_d[1:0]<=2'b0;
      rden_fifo_data0_d[31:0]<=32'b0;    
      
      rden_fifo_valid1_d<=1'b0;
      rden_fifo_sop1_d<=1'b0;
      rden_fifo_eop1_d<=1'b0;
      rden_fifo_err1_d<=1'b0;
      rden_fifo_mod1_d[1:0]<=2'b0;
      rden_fifo_data1_d[31:0]<=32'b0;
    end
  else
    begin
      rdreq0_d <=rdreq0&&~eop0;
      rdreq1_d <=rdreq1&&~eop1;
    
      rden_fifo_valid0_d<=rden_fifo_valid0;
      rden_fifo_sop0_d<=rden_fifo_sop0;
      rden_fifo_eop0_d<=rden_fifo_eop0;
      rden_fifo_err0_d<=rden_fifo_err0;
      rden_fifo_mod0_d[1:0]<=rden_fifo_mod0[1:0];
      rden_fifo_data0_d[31:0]<=rden_fifo_data0[31:0];    
      
      rden_fifo_valid1_d<=rden_fifo_valid1;
      rden_fifo_sop1_d<=rden_fifo_sop1;
      rden_fifo_eop1_d<=rden_fifo_eop1;
      rden_fifo_err1_d<=rden_fifo_err1;
      rden_fifo_mod1_d[1:0]<=rden_fifo_mod1[1:0];
      rden_fifo_data1_d[31:0]<=rden_fifo_data1[31:0];
    end
end


//output signals to pmc3386
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      a_tenb       <=1'b1;
      a_tsx        <=1'b0;
      a_tdat[31:0] <=32'h0;
      a_tsop       <=1'b0;
      a_teop       <=1'b0;
      a_terr       <=1'b0;
      a_tmod[1:0]  <=2'b0; 
      a_tprty      <=1'b0;
    end
  else if(~s_reset_n)
    begin
      a_tenb       <=1'b1;
      a_tsx        <=1'b0;
      a_tdat[31:0] <=32'h0;
      a_tsop       <=1'b0;
      a_teop       <=1'b0;
      a_terr       <=1'b0;
      a_tmod[1:0]  <=2'b0; 
      a_tprty      <=1'b0;
    end
  else if(rden_fifo_valid0 && ~rden_fifo_valid0_d)
  //else if(rdreq0_d && q0[36] && ~rden_fifo_valid0)
    begin
      a_tenb       <=1'b1;
      a_tsx        <=1'b1;
      a_tdat[31:0] <=32'h0;
      a_tsop       <=1'b0;
      a_teop       <=1'b0;
      a_terr       <=1'b0;
      a_tmod[1:0]  <=2'b0; 
      a_tprty      <=1'b0;
    end
  else if(rden_fifo_valid1 && ~rden_fifo_valid1_d)
  //else if(rdreq1_d && q1[36] && ~rden_fifo_valid1)
    begin
      a_tenb       <=1'b1;
      a_tsx        <=1'b1;
      a_tdat[31:0] <=32'h1;
      a_tsop       <=1'b0;
      a_teop       <=1'b0;
      a_terr       <=1'b0;
      a_tmod[1:0]  <=2'b0; 
      a_tprty      <=1'b0;
    end  
  else if(rden_fifo_valid0_d)                        
    begin                                              
      a_tenb       <=1'b0;                             
      a_tsx        <=1'b0;                         
      a_tdat[31:0] <=rden_fifo_data0_d[31:0];          
      a_tsop       <=rden_fifo_sop0_d;
      a_teop       <=rden_fifo_eop0_d;
      a_terr       <=rden_fifo_err0_d;
      a_tmod[1:0]  <=rden_fifo_mod0_d[1:0]; 
      a_tprty      <=1'b0;
    end
  else if(rden_fifo_valid1_d)                        
    begin                                              
      a_tenb       <=1'b0;                             
      a_tsx        <=1'b0;                         
      a_tdat[31:0] <=rden_fifo_data1_d[31:0];          
      a_tsop       <=rden_fifo_sop1_d;
      a_teop       <=rden_fifo_eop1_d;
      a_terr       <=rden_fifo_err1_d;
      a_tmod[1:0]  <=rden_fifo_mod1_d[1:0]; 
      a_tprty      <=1'b0;
    end  
  else
    begin
      a_tenb       <=1'b1;
      a_tsx        <=1'b0;
      a_tdat[31:0] <=32'h0;
      a_tsop       <=1'b0;
      a_teop       <=1'b0;
      a_terr       <=1'b0;
      a_tmod[1:0]  <=2'b0; 
      a_tprty      <=1'b0;
    end      
end  


//




endmodule