link_phy_pl3.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : link_phy_pl3.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pmc3386_tx_pl3.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13 
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module link_phy_pl3 (
	             h_reset_n,
                     s_reset_n,
                     sys_clk_100m,
	             
	             a_dtpa,
	             a_tenb,
	             a_tsx,
	             a_tdat,
	             a_tsop,
	             a_teop,
	             a_terr,
	             a_tprty,
	             a_tmod,
	             	             
	             b0_dav,
	             b0_ena,
	             b0_dat,
	             b0_sop,
	             b0_eop,
	             b0_err,
	             b0_par,
	             b0_mty,
	             
	             b1_dav,
	             b1_ena,
	             b1_dat,
	             b1_sop,
	             b1_eop,
	             b1_err,
	             b1_par,
	             b1_mty	             	             	             	             
	             );

////////////////////////////////////////////
input		h_reset_n;
input		s_reset_n;
input           sys_clk_100m;

input	[1:0]	a_dtpa;
output		a_tenb;
output		a_tsx;
output	[31:0]	a_tdat;
output		a_tsop;
output		a_teop;
output		a_terr;
output		a_tprty;
output	[1:0]	a_tmod;

output		b0_dav;
input		b0_ena;
input	[31:0]	b0_dat;
input		b0_sop;
input		b0_eop;
input		b0_err;
input		b0_par;
input	[1:0]	b0_mty;

output		b1_dav;
input		b1_ena;
input	[31:0]	b1_dat;
input		b1_sop;
input		b1_eop;
input		b1_err;
input		b1_par;
input	[1:0]	b1_mty;
/////////////////////////////////////////////
reg		a_tenb;
reg		a_tsx;
reg	[31:0]	a_tdat;
reg		a_tsop;
reg		a_teop;
reg		a_terr;
reg		a_tprty;
reg	[1:0]	a_tmod;

wire		b0_dav;
wire		b1_dav;
/////////////////////////////////////////////
//internal register
reg rdreq0;
reg rdreq1;
reg [5:0]state;

wire eop0;

reg rden_fifo_sop0;
reg rden_fifo_eop0;
reg rden_fifo_err0;
reg [1:0]rden_fifo_mod0;
reg [31:0]rden_fifo_data0;
reg rden_fifo_valid0;

wire [5:0]usedw0;
wire [36:0]q0;
wire empty0;
wire full0;

wire eop1;

reg rden_fifo_sop1;
reg rden_fifo_eop1;
reg rden_fifo_err1;
reg [1:0]rden_fifo_mod1;
reg [31:0]rden_fifo_data1;
reg rden_fifo_valid1;

wire [5:0]usedw1;
wire [36:0]q1;
wire empty1;
wire full1;

reg rdreq0_d;
reg rdreq1_d;

reg rden_fifo_sop0_d;
reg rden_fifo_eop0_d;
reg rden_fifo_err0_d;
reg [1:0]rden_fifo_mod0_d;
reg [31:0]rden_fifo_data0_d;
reg rden_fifo_valid0_d;

reg rden_fifo_sop1_d;
reg rden_fifo_eop1_d;
reg rden_fifo_err1_d;
reg [1:0]rden_fifo_mod1_d;
reg [31:0]rden_fifo_data1_d;
reg rden_fifo_valid1_d;

wire almost_full0;
wire almost_full1;
//////////////////////////////////////////////
//b0_dav
assign b0_dav = ~almost_full0;
//b1_dav
assign b1_dav = ~almost_full1;

assign eop0 = rdreq0_d ? q0[35]:1'b0;
assign eop1 = rdreq1_d ? q1[35]:1'b0;


//tx_pkt_fifo37x32
tx_pkt_fifo37x64 tx_pkt_fifo37x64_0 (
	.data({b0_sop,b0_eop,b0_err,b0_mty[1:0],b0_dat[31:0]}),
	.wrreq(b0_ena),	
	.rdreq(rdreq0&&~eop0),
	.clock(sys_clk_100m),
	.q(q0),
	.full(full0),
	.empty(empty0),
	.usedw(usedw0),
	.almost_full(almost_full0)
	);
	
//tx_pkt_fifo37x32
tx_pkt_fifo37x64 tx_pkt_fifo37x64_1 (
	.data({b1_sop,b1_eop,b1_err,b1_mty[1:0],b1_dat[31:0]}),
	.wrreq(b1_ena),	
	.rdreq(rdreq1&&~eop1),
	.clock(sys_clk_100m),
	.q(q1),
	.full(full1),
	.empty(empty1),
	.usedw(usedw1),
	.almost_full(almost_full1)
	);	

//rdreq0,1	
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rdreq0<=1'b0;
      rdreq1<=1'b0;       
      state[5:0]<=6'd0;     
    end
  else if(~s_reset_n)
    begin
      rdreq0<=1'b0;
      rdreq1<=1'b0;      
      state[5:0]<=6'd0;
    end
  else
    begin
      case(state[5:0])
        //for rdreq0
        6'd0: begin
              if(~empty0&&a_dtpa[0])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd1;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              end
        6'd1: begin
              if(~empty0&&a_dtpa[0])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd2;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              end
        6'd2: begin
              if(~empty0&&a_dtpa[0])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd3;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              end
        6'd3,
        6'd4,
        6'd5,
        6'd6,
        6'd7,
        6'd8,
        6'd9,
        6'd10,
        6'd11,
        6'd12,
        6'd13,
        6'd14,
        6'd15,
        6'd16,
        6'd17: begin
              if(~empty0&&a_dtpa[0]&&~eop0)
                begin
                  rdreq0<=1'b1;
                  rdreq1<=1'b0;
                  state[5:0]<=state[5:0] + 6'd1;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              end
        6'd18: begin
              if(~empty0&&a_dtpa[0])
                begin
                  rdreq0<=1'b1;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd19;
                end
              end
        //for rdreq1
        6'd19: begin
              if(~empty1&&a_dtpa[1])
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd20;
                end
              else
                begin
                  rdreq0<=1'b0;
                  rdreq1<=1'b0;
                  state[5:0]<=6'd0;
                end
              end
        6'd20: begin