pmc5382_to_pmc3386_pl3.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : pmc5382_to_pmc3386_pl3.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pl3_fpga_top.v
// calls to   : pmc5382_rx_pl3.v
//              pmc3386_tx_pl3.v
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13 
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module pmc5382_to_pmc3386_pl3(
                              //system signals
                              h_reset_n,
                              s_reset_n,
                              sys_clk_100m,
                                                    
                              //signals from pmc5382 block
                              pmc5382_renb,
                              pmc5382_rsx,                       
                              pmc5382_rval,
                              
                              pmc5382_rdat,                      
                              pmc5382_rsop,
                              pmc5382_reop,
                              pmc5382_rmod,
                              pmc5382_rerr,
                              pmc5382_rprty,
                                                                                                                                                                                                                                     
                              //signals to pmc3386_0 block 
                              pmc3386_tenb_0,
                              pmc3386_tsx_0,
                              pmc3386_tadr_0, 
                              pmc3386_ptpa_0,
                              pmc3386_stpa_0,
                              pmc3386_dtpa_0,                      
                              
                              
                              pmc3386_tdat_0,                      
                              pmc3386_tsop_0,
                              pmc3386_teop_0,
                              pmc3386_tmod_0,
                              pmc3386_terr_0,
                              pmc3386_tprty_0,
                              
                              //signals to pmc3386_1 block 
                              pmc3386_tenb_1,
                              pmc3386_tsx_1,
                              pmc3386_tadr_1, 
                              pmc3386_ptpa_1,
                              pmc3386_stpa_1,
                              pmc3386_dtpa_1,                      
                              
                              
                              pmc3386_tdat_1,                      
                              pmc3386_tsop_1,
                              pmc3386_teop_1,
                              pmc3386_tmod_1,
                              pmc3386_terr_1,
                              pmc3386_tprty_1,
                                     
                              //signals from m_bus block
                              header_length,
                              crc_length,
                              ge0_da_mac,
                              ge0_sa_mac,
                              ge1_da_mac,
                              ge1_sa_mac,
                              ge2_da_mac,
                              ge2_sa_mac,
                              ge3_da_mac,
                              ge3_sa_mac,

                              lose_pkt_cnt_0,
                              lose_pkt_cnt_1,
                              lose_pkt_cnt_2,
                              lose_pkt_cnt_3,
                              lose_pkt_cnt_4,
                              lose_pkt_cnt_5,
                              lose_pkt_cnt_6,
                              lose_pkt_cnt_7,
                              lose_pkt_cnt_8,
                              lose_pkt_cnt_9,
                              lose_pkt_cnt_10,
                              lose_pkt_cnt_11,
                              lose_pkt_cnt_12,
                              lose_pkt_cnt_13,
                              lose_pkt_cnt_14,
                              lose_pkt_cnt_15,
                                                                                                                              
                              //test signals
                              test_sel,
                              test_point                 
                              );
                       
                       
//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;
                      
//signals from pmc5382 block
output pmc5382_renb;
input  pmc5382_rsx;                       
input  pmc5382_rval;

input [31:0]pmc5382_rdat;                      
input       pmc5382_rsop;
input       pmc5382_reop;
input  [1:0]pmc5382_rmod;
input       pmc5382_rerr;
input       pmc5382_rprty;
                                                                                                                                                                                                       
//signals to pmc3386_0 block 
output pmc3386_tenb_0;
output pmc3386_tsx_0;
output pmc3386_tadr_0; 
input  pmc3386_ptpa_0;
input  pmc3386_stpa_0;
input  [1:0]pmc3386_dtpa_0;                      


output [31:0]pmc3386_tdat_0;                      
output       pmc3386_tsop_0;
output       pmc3386_teop_0;
output  [1:0]pmc3386_tmod_0;
output       pmc3386_terr_0;
output       pmc3386_tprty_0;

//signals to pmc3386_1 block 
output pmc3386_tenb_1;
output pmc3386_tsx_1;
output pmc3386_tadr_1; 
input  pmc3386_ptpa_1;
input  pmc3386_stpa_1;
input  [1:0]pmc3386_dtpa_1;                      


output [31:0]pmc3386_tdat_1;                      
output       pmc3386_tsop_1;
output       pmc3386_teop_1;
output  [1:0]pmc3386_tmod_1;
output       pmc3386_terr_1;
output       pmc3386_tprty_1;

//signals from m_bus block
input header_length;
input crc_length;
input [47:0]ge0_da_mac;
input [47:0]ge0_sa_mac;
input [47:0]ge1_da_mac;
input [47:0]ge1_sa_mac;
input [47:0]ge2_da_mac;
input [47:0]ge2_sa_mac;
input [47:0]ge3_da_mac;
input [47:0]ge3_sa_mac;

output [15:0]lose_pkt_cnt_0;
output [15:0]lose_pkt_cnt_1;
output [15:0]lose_pkt_cnt_2;
output [15:0]lose_pkt_cnt_3;
output [15:0]lose_pkt_cnt_4;
output [15:0]lose_pkt_cnt_5;
output [15:0]lose_pkt_cnt_6;
output [15:0]lose_pkt_cnt_7;
output [15:0]lose_pkt_cnt_8;
output [15:0]lose_pkt_cnt_9;
output [15:0]lose_pkt_cnt_10;
output [15:0]lose_pkt_cnt_11;
output [15:0]lose_pkt_cnt_12;
output [15:0]lose_pkt_cnt_13;
output [15:0]lose_pkt_cnt_14;
output [15:0]lose_pkt_cnt_15;
                                                                                                       
//test signals
input   [7:0]test_sel;
output [31:0]test_point;

/////////////////////////////////////////////
reg [31:0]test_point;

/////////////////////////////////////////////////////////////////////////////////////////
//internal signals 
wire ch0_fifo_aval;
wire ch1_fifo_aval;
wire ch2_fifo_aval;
wire ch3_fifo_aval;
wire ch4_fifo_aval;
wire ch5_fifo_aval;
wire ch6_fifo_aval;
wire ch7_fifo_aval;
wire ch8_fifo_aval;
wire ch9_fifo_aval;
wire ch10_fifo_aval;
wire ch11_fifo_aval;
wire ch12_fifo_aval;         
wire ch13_fifo_aval;
wire ch14_fifo_aval;
wire ch15_fifo_aval;

wire ch0_fifo_rden;
wire ch1_fifo_rden;
wire ch2_fifo_rden;
wire ch3_fifo_rden;
wire ch4_fifo_rden;
wire ch5_fifo_rden;
wire ch6_fifo_rden;
wire ch7_fifo_rden;
wire ch8_fifo_rden;
wire ch9_fifo_rden;
wire ch10_fifo_rden;
wire ch11_fifo_rden;
wire ch12_fifo_rden;
wire ch13_fifo_rden;
wire ch14_fifo_rden;
wire ch15_fifo_rden;

//ch0
wire [31:0]ch0_fifo_data;
wire       ch0_fifo_sop;
wire       ch0_fifo_eop;
wire  [1:0]ch0_fifo_mod;
wire       ch0_fifo_err;
wire       ch0_fifo_par; 
//ch1
wire [31:0]ch1_fifo_data;
wire       ch1_fifo_sop;
wire       ch1_fifo_eop;
wire  [1:0]ch1_fifo_mod;
wire       ch1_fifo_err; 
wire       ch1_fifo_par;
//ch2
wire [31:0]ch2_fifo_data;
wire       ch2_fifo_sop;
wire       ch2_fifo_eop;
wire  [1:0]ch2_fifo_mod;
wire       ch2_fifo_err; 
wire       ch2_fifo_par;
//ch3
wire [31:0]ch3_fifo_data;