rx_pkt_fifo_pro.v

VERILOG五POSPHY LEVEL3电路描述

//**************************************************************************************************************************************
// +fhdr---------------------------------------------------------------------------------------------------------------
// copyright (c) 2005,xws.
// xws confidential proprietary
// --------------------------------------------------------------------------------------------------------------------
// project    : pos_phy fpga 
// file name  : rx_pkt_fifo_pro.v
// directory  : 
// type       : synthesisable rtl code , verilog
// called by  : pl3_fpga_top.v
// calls to   : 
//              
//              
//              
// version    : ver1.0
// --------------------------------------------------------------------------------------------------------------------
// author     : xws
// e-mail     : [e-mail] 
// department : R&D center
// --------------------------------------------------------------------------------------------------------------------
// purpose    :  
// function   : 
// creatdate  : 2005-09-13 
// updatedate : 
// history    : 
// clock domains:   100MHz
// reset strategy:  
// see also:
// detail description: 
// --------------------------------------------------------------------------------------------------------------------
// keywords   :
// -fhdr---------------------------------------------------------------------------------------------------------------
//*************************************************************************************************************************************
`include "define.v"

module rx_pkt_fifo_pro(
                      //system signals
                      h_reset_n,
                      s_reset_n,
                      sys_clk_100m,
                      
                      //signals
                      wren_fifo_sop,
                      wren_fifo_eop,
                      wren_fifo_err,
                      wren_fifo_mod,
                      wren_fifo_data,
                      wren_fifo_val,
                      //
                      rden_fifo_sop,
                      rden_fifo_eop,
                      rden_fifo_err,
                      rden_fifo_mod,
                      rden_fifo_data,
                      rden_fifo_val, 
                                                                                                                                                                                                                                                                                                                                                                 
                      //test signals
                      test_sel,
                      test_point                 
                      );
                       
                       
//system signals
input h_reset_n;
input s_reset_n;
input sys_clk_100m;

//signals
input wren_fifo_sop;
input wren_fifo_eop;
input wren_fifo_err;
input [1:0]wren_fifo_mod;
input [31:0]wren_fifo_data;
input wren_fifo_val;
//
output rden_fifo_sop;
output rden_fifo_eop;
output rden_fifo_err;
output [1:0]rden_fifo_mod;
output [31:0]rden_fifo_data;
output rden_fifo_val; 
                                                                                          
//test signals
input [7:0]test_sel;
output [31:0]test_point; 

///////////////////////////////////////////////
wire [31:0]test_point;

reg rden_fifo_sop;
reg rden_fifo_eop;
reg rden_fifo_err;
reg [1:0]rden_fifo_mod;
reg [31:0]rden_fifo_data;
reg rden_fifo_val;

////////////////////////////////////
wire [36:0]q;
wire full;
wire empty;
reg rden_fifo_val_tmp;
wire eop;
reg eop_d,eop_2d,eop_3d;

wire [3:0]usedw;
reg fifo_ena;
////////////////////////////////////////////////////////
assign test_point = 32'b0;




assign eop = rden_fifo_val_tmp ? q[35]:1'b0;

always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      eop_d <=1'b0;
      eop_2d<=1'b0;
      eop_3d<=1'b0; 
    end
  else if(~s_reset_n)
    begin
      eop_d <=1'b0;
      eop_2d<=1'b0;
      eop_3d<=1'b0;
    end
  else
    begin
      eop_d <=eop;
      eop_2d<=eop_d;
      eop_3d<=eop_2d;
    end
end

//rx_pkt_fifo37x16
rx_pkt_fifo37x16 rx_pkt_fifo37x16 (
	.data({wren_fifo_sop,wren_fifo_eop,wren_fifo_err,wren_fifo_mod[1:0],wren_fifo_data[31:0]}),
	.wrreq(wren_fifo_val),
	//.rdreq(~empty&&~eop&&~eop_d&&~eop_2d&&~eop_3d),
	.rdreq(((usedw>=4'd5)||fifo_ena)&&~eop&&~eop_d&&~eop_2d&&~eop_3d),
	.clock(sys_clk_100m),
	.q(q),
	.full(full),
	.empty(empty),
	.usedw(usedw)
	);
	
//fifo_ena
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      fifo_ena<=1'b0;      
    end
  else if(~s_reset_n)
    begin
      fifo_ena<=1'b0;
    end
  else if(wren_fifo_eop)
    begin
      fifo_ena<=1'b1;
    end
  else if(rden_fifo_eop)
    begin
      fifo_ena<=1'b0;
    end
  else
    begin
      fifo_ena<=fifo_ena;
    end
end	
//rden_fifo_val_tmp	
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rden_fifo_val_tmp<=1'b0; 
    end
  else if(~s_reset_n)
    begin
      rden_fifo_val_tmp<=1'b0;  
    end
  //else if(~empty&&~eop&&~eop_d&&~eop_2d&&~eop_3d)
  else if(((usedw>=4'd5)||fifo_ena)&&~eop&&~eop_d&&~eop_2d&&~eop_3d)
    begin
      rden_fifo_val_tmp<=1'b1; 
    end
  else
    begin
      rden_fifo_val_tmp<=1'b0; 
    end
end

//output signals
always @(posedge sys_clk_100m or negedge h_reset_n or negedge s_reset_n)
begin
  if(~h_reset_n)
    begin
      rden_fifo_sop<=1'b0;
      rden_fifo_eop<=1'b0;
      rden_fifo_err<=1'b0;
      rden_fifo_mod[1:0]<=2'b0;
      rden_fifo_data[31:0]<=32'b0;
      rden_fifo_val<=1'b0;
    end
  else if(~s_reset_n)
    begin
      rden_fifo_sop<=1'b0;
      rden_fifo_eop<=1'b0;
      rden_fifo_err<=1'b0;
      rden_fifo_mod[1:0]<=2'b0;
      rden_fifo_data[31:0]<=32'b0;
      rden_fifo_val<=1'b0;  
    end
  else if(rden_fifo_val_tmp)
    begin
      rden_fifo_sop<=q[36];
      rden_fifo_eop<=q[35];
      rden_fifo_err<=q[34];
      rden_fifo_mod[1:0]<=q[33:32];
      rden_fifo_data[31:0]<=q[31:0];
      rden_fifo_val<=1'b1;  
    end
  else
    begin
      rden_fifo_sop<=1'b0;
      rden_fifo_eop<=1'b0;
      rden_fifo_err<=1'b0;
      rden_fifo_mod[1:0]<=2'b0;
      rden_fifo_data[31:0]<=32'b0;
      rden_fifo_val<=1'b0;
    end
end 

endmodule