link_phy_pl3.bsf

VERILOG五POSPHY LEVEL3电路描述

/*
Generated through CNX2HDL Converter version 1.1
*/
/*
Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
************************************************************
THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
************************************************************
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*/
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