link_phy_pl3.v

VERILOG五POSPHY LEVEL3电路描述

	wire [31:0] signal_wire124 = 32'b00000000000000000000000000001001;
	wire [31:0] signal_wire125 = 32'b00000000000000000000000000001010;
	wire [31:0] signal_wire126 = 32'b00000000000000000000000000001011;
	wire [31:0] signal_wire127 = 32'b00000000000000000000000000001100;
	wire [31:0] signal_wire128 = 32'b00000000000000000000000000001101;
	wire [31:0] signal_wire129 = 32'b00000000000000000000000000001110;
	wire [31:0] signal_wire130 = 32'b00000000000000000000000000001111;
	wire [31:0] signal_wire131 = 32'b00000000000000000000000000010000;
	wire [31:0] signal_wire132 = 32'b00000000000000000000000000010001;

	auk_pac_mtx_mw	auk_pac_mtx_mw_inst(
		.clka(a_tfclk),
		.reseta(a_treset_n),
		.dpav_ina(a_dtpa),
		.ppav_ina(signal_wire0),
		.spav_ina(signal_wire1),
		.addr_ina(signal_wire2),
		.rd_ina(signal_wire3),
		.clkb1(b_clk),
		.resetb1(b_reset_n),
		.dpav_inb1(signal_wire4),
		.ppav_inb1(signal_wire5),
		.spav_inb1(signal_wire6),
		.dav_inb1(signal_wire7),
		.addr_inb1(signal_wire8),
		.wr_inb1(b1_ena),
		.val_inb1(signal_wire9),
		.sx_inb1(signal_wire10),
		.data_inb1(b1_dat),
		.sop_inb1(b1_sop),
		.eop_inb1(b1_eop),
		.err_inb1(b1_err),
		.prty_inb1(signal_wire11),
		.mod_inb1(b1_mty),
		.clkb2(b_clk),
		.resetb2(b_reset_n),
		.dpav_inb2(signal_wire12),
		.ppav_inb2(signal_wire13),
		.spav_inb2(signal_wire14),
		.dav_inb2(signal_wire15),
		.addr_inb2(signal_wire16),
		.wr_inb2(b2_ena),
		.val_inb2(signal_wire17),
		.sx_inb2(signal_wire18),
		.data_inb2(b2_dat),
		.sop_inb2(b2_sop),
		.eop_inb2(b2_eop),
		.err_inb2(b2_err),
		.prty_inb2(signal_wire19),
		.mod_inb2(b2_mty),
		.clkb3(signal_wire20),
		.resetb3(signal_wire21),
		.dpav_inb3(signal_wire22),
		.ppav_inb3(signal_wire23),
		.spav_inb3(signal_wire24),
		.dav_inb3(signal_wire25),
		.addr_inb3(signal_wire26),
		.wr_inb3(signal_wire27),
		.val_inb3(signal_wire28),
		.sx_inb3(signal_wire29),
		.data_inb3(signal_wire30),
		.sop_inb3(signal_wire31),
		.eop_inb3(signal_wire32),
		.err_inb3(signal_wire33),
		.prty_inb3(signal_wire34),
		.mod_inb3(signal_wire35),
		.clkb4(signal_wire36),
		.resetb4(signal_wire37),
		.dpav_inb4(signal_wire38),
		.ppav_inb4(signal_wire39),
		.spav_inb4(signal_wire40),
		.dav_inb4(signal_wire41),
		.addr_inb4(signal_wire42),
		.wr_inb4(signal_wire43),
		.val_inb4(signal_wire44),
		.sx_inb4(signal_wire45),
		.data_inb4(signal_wire46),
		.sop_inb4(signal_wire47),
		.eop_inb4(signal_wire48),
		.err_inb4(signal_wire49),
		.prty_inb4(signal_wire50),
		.mod_inb4(signal_wire51),
		.clkb5(signal_wire52),
		.resetb5(signal_wire53),
		.dpav_inb5(signal_wire54),
		.ppav_inb5(signal_wire55),
		.spav_inb5(signal_wire56),
		.dav_inb5(signal_wire57),
		.addr_inb5(signal_wire58),
		.wr_inb5(signal_wire59),
		.val_inb5(signal_wire60),
		.sx_inb5(signal_wire61),
		.data_inb5(signal_wire62),
		.sop_inb5(signal_wire63),
		.eop_inb5(signal_wire64),
		.err_inb5(signal_wire65),
		.prty_inb5(signal_wire66),
		.mod_inb5(signal_wire67),
		.clkb6(signal_wire68),
		.resetb6(signal_wire69),
		.dpav_inb6(signal_wire70),
		.ppav_inb6(signal_wire71),
		.spav_inb6(signal_wire72),
		.dav_inb6(signal_wire73),
		.addr_inb6(signal_wire74),
		.wr_inb6(signal_wire75),
		.val_inb6(signal_wire76),
		.sx_inb6(signal_wire77),
		.data_inb6(signal_wire78),
		.sop_inb6(signal_wire79),
		.eop_inb6(signal_wire80),
		.err_inb6(signal_wire81),
		.prty_inb6(signal_wire82),
		.mod_inb6(signal_wire83),
		.clkb7(signal_wire84),
		.resetb7(signal_wire85),
		.dpav_inb7(signal_wire86),
		.ppav_inb7(signal_wire87),
		.spav_inb7(signal_wire88),
		.dav_inb7(signal_wire89),
		.addr_inb7(signal_wire90),
		.wr_inb7(signal_wire91),
		.val_inb7(signal_wire92),
		.sx_inb7(signal_wire93),
		.data_inb7(signal_wire94),
		.sop_inb7(signal_wire95),
		.eop_inb7(signal_wire96),
		.err_inb7(signal_wire97),
		.prty_inb7(signal_wire98),
		.mod_inb7(signal_wire99),
		.clkb8(signal_wire100),
		.resetb8(signal_wire101),
		.dpav_inb8(signal_wire102),
		.ppav_inb8(signal_wire103),
		.spav_inb8(signal_wire104),
		.dav_inb8(signal_wire105),
		.addr_inb8(signal_wire106),
		.wr_inb8(signal_wire107),
		.val_inb8(signal_wire108),
		.sx_inb8(signal_wire109),
		.data_inb8(signal_wire110),
		.sop_inb8(signal_wire111),
		.eop_inb8(signal_wire112),
		.err_inb8(signal_wire113),
		.prty_inb8(signal_wire114),
		.mod_inb8(signal_wire115),
		.custom_ina0(signal_wire116),
		.custom_ina1(signal_wire117),
		.custom_inb1(signal_wire118),
		.custom_ina2(signal_wire119),
		.custom_inb2(signal_wire120),
		.custom_ina3(signal_wire121),
		.custom_inb3(signal_wire122),
		.custom_ina4(signal_wire123),
		.custom_inb4(signal_wire124),
		.custom_ina5(signal_wire125),
		.custom_inb5(signal_wire126),
		.custom_ina6(signal_wire127),
		.custom_inb6(signal_wire128),
		.custom_ina7(signal_wire129),
		.custom_inb7(signal_wire130),
		.custom_ina8(signal_wire131),
		.custom_inb8(signal_wire132),
		.wr_outa(a_tenb),
		.sx_outa(a_tsx),
		.data_outa(a_tdat),
		.sop_outa(a_tsop),
		.eop_outa(a_teop),
		.err_outa(a_terr),
		.mod_outa(a_tmod),
		.dav_outb1(b1_dav),
		.dav_outb2(b2_dav));

	defparam
		auk_pac_mtx_mw_inst.gio_number_of_interface_a = 1,
		auk_pac_mtx_mw_inst.gio_number_of_interface_b = 2,
		auk_pac_mtx_mw_inst.gio_number_of_fifo = 1,
		auk_pac_mtx_mw_inst.gio_bus_mode = "1 2 2",
		auk_pac_mtx_mw_inst.gio_bus_level = "2 2 2",
		auk_pac_mtx_mw_inst.gio_bus_type = "0 1 1",
		auk_pac_mtx_mw_inst.gio_bus_direction = "0 1 1",
		auk_pac_mtx_mw_inst.gio_address_channels = "2 1 1",
		auk_pac_mtx_mw_inst.gio_address_range = "2 1 1",
		auk_pac_mtx_mw_inst.gio_address_width = "1 0 0",
		auk_pac_mtx_mw_inst.gio_address_style = "0 0 0",
		auk_pac_mtx_mw_inst.gio_base_address = "0 0 0",
		auk_pac_mtx_mw_inst.gio_address_mask = "0 0 0",
		auk_pac_mtx_mw_inst.gio_transfer_mode = "0 0 0",
		auk_pac_mtx_mw_inst.gio_dpav_range = "2 0 0",
		auk_pac_mtx_mw_inst.gio_spav_present = "1 1 0",
		auk_pac_mtx_mw_inst.gio_ppav_present = "0 0 0",
		auk_pac_mtx_mw_inst.gio_ddav_range = "2 1 1",
		auk_pac_mtx_mw_inst.gio_sx_present = "1 0 0",
		auk_pac_mtx_mw_inst.gio_val_present = "1 1 1",
		auk_pac_mtx_mw_inst.gio_eop_present = "1 1 1",
		auk_pac_mtx_mw_inst.gio_mod_present = "1 1 1",
		auk_pac_mtx_mw_inst.gio_data_width = "32 32 32",
		auk_pac_mtx_mw_inst.gio_prty_error_mode = "1 1 1",
		auk_pac_mtx_mw_inst.gio_prty_present = "0 0 0",
		auk_pac_mtx_mw_inst.gio_prty_mode = "0 0 0",
		auk_pac_mtx_mw_inst.gfifo_addr_range = "0 0 0",
		auk_pac_mtx_mw_inst.gfifo_depth = "0 64 64",
		auk_pac_mtx_mw_inst.gfifo_sync = "0 0 0",
		auk_pac_mtx_mw_inst.gio_fifo_burst = "8 8 8",
		auk_pac_mtx_mw_inst.gio_remote_burst = "8 8 8",
		auk_pac_mtx_mw_inst.gio_full_on_thresh = "0 11 11",
		auk_pac_mtx_mw_inst.gio_full_off_thresh = "0 11 11",
		auk_pac_mtx_mw_inst.gio_empty_on_thresh = "0 0 0",
		auk_pac_mtx_mw_inst.gio_empty_off_thresh = "0 8 8",
		auk_pac_mtx_mw_inst.gio_master_full_thresh = "0 5 5",
		auk_pac_mtx_mw_inst.gio_master_empty_thresh = "0 0 0",