link_phy_pl3.v

VERILOG五POSPHY LEVEL3电路描述

// megafunction wizard: %POS-PHY Level 2 and 3 Compiler v1.3.1%

// ============================================================
// Megafunction Name(s):
// 			auk_pac_mtx_mw
// ============================================================
// Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.


module link_phy_pl3 (
	a_tfclk,
	a_treset_n,
	a_dtpa,
	b_clk,
	b_reset_n,
	b1_ena,
	b1_dat,
	b1_sop,
	b1_eop,
	b1_err,
	b1_mty,
	b2_ena,
	b2_dat,
	b2_sop,
	b2_eop,
	b2_err,
	b2_mty,
	a_tenb,
	a_tsx,
	a_tdat,
	a_tsop,
	a_teop,
	a_terr,
	a_tmod,
	b1_dav,
	b2_dav);


	input		a_tfclk;
	input		a_treset_n;
	input	[1:0]	a_dtpa;
	input		b_clk;
	input		b_reset_n;
	input		b1_ena;
	input	[31:0]	b1_dat;
	input		b1_sop;
	input		b1_eop;
	input		b1_err;
	input	[1:0]	b1_mty;
	input		b2_ena;
	input	[31:0]	b2_dat;
	input		b2_sop;
	input		b2_eop;
	input		b2_err;
	input	[1:0]	b2_mty;
	output		a_tenb;
	output		a_tsx;
	output	[31:0]	a_tdat;
	output		a_tsop;
	output		a_teop;
	output		a_terr;
	output	[1:0]	a_tmod;
	output		b1_dav;
	output		b2_dav;

	wire signal_wire0 = 1'b0;
	wire signal_wire1 = 1'b0;
	wire [7:0] signal_wire2 = 8'b0;
	wire signal_wire3 = 1'b0;
	wire [7:0] signal_wire4 = 8'b0;
	wire signal_wire5 = 1'b0;
	wire signal_wire6 = 1'b0;
	wire signal_wire7 = 1'b0;
	wire [7:0] signal_wire8 = 8'b0;
	wire signal_wire9 = 1'b0;
	wire signal_wire10 = 1'b0;
	wire signal_wire11 = 1'b0;
	wire [7:0] signal_wire12 = 8'b0;
	wire signal_wire13 = 1'b0;
	wire signal_wire14 = 1'b0;
	wire signal_wire15 = 1'b0;
	wire [7:0] signal_wire16 = 8'b0;
	wire signal_wire17 = 1'b0;
	wire signal_wire18 = 1'b0;
	wire signal_wire19 = 1'b0;
	wire signal_wire20 = 1'b0;
	wire signal_wire21 = 1'b0;
	wire [7:0] signal_wire22 = 8'b0;
	wire signal_wire23 = 1'b0;
	wire signal_wire24 = 1'b0;
	wire signal_wire25 = 1'b0;
	wire [7:0] signal_wire26 = 8'b0;
	wire signal_wire27 = 1'b0;
	wire signal_wire28 = 1'b0;
	wire signal_wire29 = 1'b0;
	wire [63:0] signal_wire30 = 64'b0;
	wire signal_wire31 = 1'b0;
	wire signal_wire32 = 1'b0;
	wire signal_wire33 = 1'b0;
	wire signal_wire34 = 1'b0;
	wire [3:0] signal_wire35 = 4'b0;
	wire signal_wire36 = 1'b0;
	wire signal_wire37 = 1'b0;
	wire [7:0] signal_wire38 = 8'b0;
	wire signal_wire39 = 1'b0;
	wire signal_wire40 = 1'b0;
	wire signal_wire41 = 1'b0;
	wire [7:0] signal_wire42 = 8'b0;
	wire signal_wire43 = 1'b0;
	wire signal_wire44 = 1'b0;
	wire signal_wire45 = 1'b0;
	wire [63:0] signal_wire46 = 64'b0;
	wire signal_wire47 = 1'b0;
	wire signal_wire48 = 1'b0;
	wire signal_wire49 = 1'b0;
	wire signal_wire50 = 1'b0;
	wire [3:0] signal_wire51 = 4'b0;
	wire signal_wire52 = 1'b0;
	wire signal_wire53 = 1'b0;
	wire [7:0] signal_wire54 = 8'b0;
	wire signal_wire55 = 1'b0;
	wire signal_wire56 = 1'b0;
	wire signal_wire57 = 1'b0;
	wire [7:0] signal_wire58 = 8'b0;
	wire signal_wire59 = 1'b0;
	wire signal_wire60 = 1'b0;
	wire signal_wire61 = 1'b0;
	wire [63:0] signal_wire62 = 64'b0;
	wire signal_wire63 = 1'b0;
	wire signal_wire64 = 1'b0;
	wire signal_wire65 = 1'b0;
	wire signal_wire66 = 1'b0;
	wire [3:0] signal_wire67 = 4'b0;
	wire signal_wire68 = 1'b0;
	wire signal_wire69 = 1'b0;
	wire [7:0] signal_wire70 = 8'b0;
	wire signal_wire71 = 1'b0;
	wire signal_wire72 = 1'b0;
	wire signal_wire73 = 1'b0;
	wire [7:0] signal_wire74 = 8'b0;
	wire signal_wire75 = 1'b0;
	wire signal_wire76 = 1'b0;
	wire signal_wire77 = 1'b0;
	wire [63:0] signal_wire78 = 64'b0;
	wire signal_wire79 = 1'b0;
	wire signal_wire80 = 1'b0;
	wire signal_wire81 = 1'b0;
	wire signal_wire82 = 1'b0;
	wire [3:0] signal_wire83 = 4'b0;
	wire signal_wire84 = 1'b0;
	wire signal_wire85 = 1'b0;
	wire [7:0] signal_wire86 = 8'b0;
	wire signal_wire87 = 1'b0;
	wire signal_wire88 = 1'b0;
	wire signal_wire89 = 1'b0;
	wire [7:0] signal_wire90 = 8'b0;
	wire signal_wire91 = 1'b0;
	wire signal_wire92 = 1'b0;
	wire signal_wire93 = 1'b0;
	wire [63:0] signal_wire94 = 64'b0;
	wire signal_wire95 = 1'b0;
	wire signal_wire96 = 1'b0;
	wire signal_wire97 = 1'b0;
	wire signal_wire98 = 1'b0;
	wire [3:0] signal_wire99 = 4'b0;
	wire signal_wire100 = 1'b0;
	wire signal_wire101 = 1'b0;
	wire [7:0] signal_wire102 = 8'b0;
	wire signal_wire103 = 1'b0;
	wire signal_wire104 = 1'b0;
	wire signal_wire105 = 1'b0;
	wire [7:0] signal_wire106 = 8'b0;
	wire signal_wire107 = 1'b0;
	wire signal_wire108 = 1'b0;
	wire signal_wire109 = 1'b0;
	wire [63:0] signal_wire110 = 64'b0;
	wire signal_wire111 = 1'b0;
	wire signal_wire112 = 1'b0;
	wire signal_wire113 = 1'b0;
	wire signal_wire114 = 1'b0;
	wire [3:0] signal_wire115 = 4'b0;
	wire [31:0] signal_wire116 = 32'b00000000000000000000000000000001;
	wire [31:0] signal_wire117 = 32'b00000000000000000000000000000010;
	wire [31:0] signal_wire118 = 32'b00000000000000000000000000000011;
	wire [31:0] signal_wire119 = 32'b00000000000000000000000000000100;
	wire [31:0] signal_wire120 = 32'b00000000000000000000000000000101;
	wire [31:0] signal_wire121 = 32'b00000000000000000000000000000110;
	wire [31:0] signal_wire122 = 32'b00000000000000000000000000000111;
	wire [31:0] signal_wire123 = 32'b00000000000000000000000000001000;