link_phy_pl3_bb.v

VERILOG五POSPHY LEVEL3电路描述

// Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// support information, device programming or simulation file, and any other
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// programming or simulation file, or any other related documentation or
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module link_phy_pl3 (
	a_tfclk,
	a_treset_n,
	a_dtpa,
	b_clk,
	b_reset_n,
	b1_ena,
	b1_dat,
	b1_sop,
	b1_eop,
	b1_err,
	b1_mty,
	b2_ena,
	b2_dat,
	b2_sop,
	b2_eop,
	b2_err,
	b2_mty,
	a_tenb,
	a_tsx,
	a_tdat,
	a_tsop,
	a_teop,
	a_terr,
	a_tmod,
	b1_dav,
	b2_dav);

	input		a_tfclk;
	input		a_treset_n;
	input	[1:0]	a_dtpa;
	input		b_clk;
	input		b_reset_n;
	input		b1_ena;
	input	[31:0]	b1_dat;
	input		b1_sop;
	input		b1_eop;
	input		b1_err;
	input	[1:0]	b1_mty;
	input		b2_ena;
	input	[31:0]	b2_dat;
	input		b2_sop;
	input		b2_eop;
	input		b2_err;
	input	[1:0]	b2_mty;
	output		a_tenb;
	output		a_tsx;
	output	[31:0]	a_tdat;
	output		a_tsop;
	output		a_teop;
	output		a_terr;
	output	[1:0]	a_tmod;
	output		b1_dav;
	output		b2_dav;
endmodule