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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - POS-PHY Level 2 and 3 Compiler v1.3.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>auk_pac_mtx_mw</TD></TR><TR><TD><B>Variation Name</B></TD><TD>link_phy_pl3</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>F:\POS_phy\POS_PHY_RTL\link_phy_slave</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>link_phy_pl3.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>link_phy_pl3_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>link_phy_pl3.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>link_phy_pl3.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>link_phy_pl3_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>link_phy_pl3.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>link_phy_pl3.vo</TD><TD>Verilog HDL IP functional simulation model.</TD></TR><TR><TD>link_phy_pl3.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Parameters</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Value</B></TH></TR><TR ><TD>gio_number_of_interface_a</TD><TD>1</TD></TR><TR ><TD>gio_number_of_interface_b</TD><TD>2</TD></TR><TR ><TD>gio_number_of_fifo</TD><TD>1</TD></TR><TR ><TD>gio_bus_mode</TD><TD>1 2 2</TD></TR><TR ><TD>gio_bus_level</TD><TD>2 2 2</TD></TR><TR ><TD>gio_bus_type</TD><TD>0 1 1</TD></TR><TR ><TD>gio_bus_direction</TD><TD>0 1 1</TD></TR><TR ><TD>gio_address_channels</TD><TD>2 1 1</TD></TR><TR ><TD>gio_address_range</TD><TD>2 1 1</TD></TR><TR ><TD>gio_address_width</TD><TD>1 0 0</TD></TR><TR ><TD>gio_address_style</TD><TD>0 0 0</TD></TR><TR ><TD>gio_base_address</TD><TD>0 0 0</TD></TR><TR ><TD>gio_address_mask</TD><TD>0 0 0</TD></TR><TR ><TD>gio_transfer_mode</TD><TD>0 0 0</TD></TR><TR ><TD>gio_dpav_range</TD><TD>2 0 0</TD></TR><TR ><TD>gio_spav_present</TD><TD>1 1 0</TD></TR><TR ><TD>gio_ppav_present</TD><TD>0 0 0</TD></TR><TR ><TD>gio_ddav_range</TD><TD>2 1 1</TD></TR><TR ><TD>gio_sx_present</TD><TD>1 0 0</TD></TR><TR ><TD>gio_val_present</TD><TD>1 1 1</TD></TR><TR ><TD>gio_eop_present</TD><TD>1 1 1</TD></TR><TR ><TD>gio_mod_present</TD><TD>1 1 1</TD></TR><TR ><TD>gio_data_width</TD><TD>32 32 32</TD></TR><TR ><TD>gio_prty_error_mode</TD><TD>1 1 1</TD></TR><TR ><TD>gio_prty_present</TD><TD>0 0 0</TD></TR><TR ><TD>gio_prty_mode</TD><TD>0 0 0</TD></TR><TR ><TD>gfifo_addr_range</TD><TD>0 0 0</TD></TR><TR ><TD>gfifo_depth</TD><TD>0 64 64</TD></TR><TR ><TD>gfifo_sync</TD><TD>0 0 0</TD></TR><TR ><TD>gio_fifo_burst</TD><TD>8 8 8</TD></TR><TR ><TD>gio_remote_burst</TD><TD>8 8 8</TD></TR><TR ><TD>gio_full_on_thresh</TD><TD>0 11 11</TD></TR><TR ><TD>gio_full_off_thresh</TD><TD>0 11 11</TD></TR><TR ><TD>gio_empty_on_thresh</TD><TD>0 0 0</TD></TR><TR ><TD>gio_empty_off_thresh</TD><TD>0 8 8</TD></TR><TR ><TD>gio_master_full_thresh</TD><TD>0 5 5</TD></TR><TR ><TD>gio_master_empty_thresh</TD><TD>0 0 0</TD></TR><TR ><TD>gio_mux_present</TD><TD>1 0 0</TD></TR><TR ><TD>gio_conva_present</TD><TD>0 1 1</TD></TR><TR ><TD>gio_convb_present</TD><TD>0 0 0</TD></TR><TR ><TD>gfifo_present</TD><TD>0 1 1</TD></TR><TR ><TD>gio_master_rd_dav_present</TD><TD>1 1 1</TD></TR><TR ><TD>gio_master_val_in_present</TD><TD>1 1 1</TD></TR><TR ><TD>gio_master_halt_on_val</TD><TD>1 1 1</TD></TR><TR ><TD>gio_data_out_zero</TD><TD>0 0 0</TD></TR><TR ><TD>gio_dumb_mode</TD><TD>0 0 0</TD></TR><TR ><TD>gio_speculative_read</TD><TD>1 1 1</TD></TR><TR ><TD>gio_custom_mode</TD><TD>0 0 0</TD></TR><TR ><TD>gio_reset</TD><TD>0 0 0</TD></TR><TR ><TD>gdevice</TD><TD>7</TD></TR><TR ><TD>gdpav_width_in0</TD><TD>2</TD></TR><TR ><TD>gdpav_width_out0</TD><TD>2</TD></TR><TR ><TD>gaddr_width_out0</TD><TD>1</TD></TR><TR ><TD>gdata_width0</TD><TD>32</TD></TR><TR ><TD>gmod_width0</TD><TD>2</TD></TR><TR ><TD>gdpav_width_out1</TD><TD>1</TD></TR><TR ><TD>gaddr_width_out1</TD><TD>1</TD></TR><TR ><TD>gdata_width1</TD><TD>32</TD></TR><TR ><TD>gmod_width1</TD><TD>2</TD></TR><TR ><TD>gdpav_width_out2</TD><TD>1</TD></TR><TR ><TD>gaddr_width_out2</TD><TD>1</TD></TR><TR ><TD>gdata_width2</TD><TD>32</TD></TR><TR ><TD>gmod_width2</TD><TD>2</TD></TR><TR ><TD>gdpav_width_in3</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out3</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in3</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out3</TD><TD>8</TD></TR><TR ><TD>gdata_width3</TD><TD>64</TD></TR><TR ><TD>gmod_width3</TD><TD>4</TD></TR><TR ><TD>gdpav_width_in4</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out4</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in4</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out4</TD><TD>8</TD></TR><TR ><TD>gdata_width4</TD><TD>64</TD></TR><TR ><TD>gmod_width4</TD><TD>4</TD></TR><TR ><TD>gdpav_width_in5</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out5</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in5</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out5</TD><TD>8</TD></TR><TR ><TD>gdata_width5</TD><TD>64</TD></TR><TR ><TD>gmod_width5</TD><TD>4</TD></TR><TR ><TD>gdpav_width_in6</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out6</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in6</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out6</TD><TD>8</TD></TR><TR ><TD>gdata_width6</TD><TD>64</TD></TR><TR ><TD>gmod_width6</TD><TD>4</TD></TR><TR ><TD>gdpav_width_in7</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out7</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in7</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out7</TD><TD>8</TD></TR><TR ><TD>gdata_width7</TD><TD>64</TD></TR><TR ><TD>gmod_width7</TD><TD>4</TD></TR><TR ><TD>gdpav_width_in8</TD><TD>8</TD></TR><TR ><TD>gdpav_width_out8</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in8</TD><TD>8</TD></TR><TR ><TD>gaddr_width_out8</TD><TD>8</TD></TR><TR ><TD>gdata_width8</TD><TD>64</TD></TR><TR ><TD>gmod_width8</TD><TD>4</TD></TR><TR ><TD>gaddr_width_in0</TD><TD>8</TD></TR><TR ><TD>gdpav_width_in1</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in1</TD><TD>8</TD></TR><TR ><TD>gdpav_width_in2</TD><TD>8</TD></TR><TR ><TD>gaddr_width_in2</TD><TD>8</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clka</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reseta</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_ina</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ppav_ina</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_ina</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_ina</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>rd_ina</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>wr_outa</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>sx_outa</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>data_outa</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>sop_outa</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>eop_outa</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>err_outa</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mod_outa</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>clkb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb1</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb1</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb1</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>sop_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb1</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb1</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>dav_outb1</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clkb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb2</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb2</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb2</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>sop_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb2</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb2</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>dav_outb2</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>clkb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb3</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb3</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb3</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb3</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb3</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>clkb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb4</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb4</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb4</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb4</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb4</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>clkb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb5</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb5</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb5</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb5</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb5</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>clkb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb6</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb6</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb6</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb6</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb6</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>clkb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb7</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb7</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb7</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb7</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb7</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>clkb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>resetb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dpav_inb8</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ppav_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>spav_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dav_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>addr_inb8</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>wr_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>val_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sx_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_inb8</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>sop_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>eop_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>err_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>prty_inb8</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>mod_inb8</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>custom_ina0</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina1</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb1</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina2</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb2</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina3</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb3</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina4</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb4</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina5</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb5</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina6</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb6</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina7</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb7</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_ina8</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>custom_inb8</TD><TD>INPUT</TD><TD>32</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 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