link_phy_pl3.cmp

VERILOG五POSPHY LEVEL3电路描述

-- Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
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-- support information, device programming or simulation file, and any other
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component link_phy_pl3
	PORT (
		a_tfclk	: IN STD_LOGIC;
		a_treset_n	: IN STD_LOGIC;
		a_dtpa	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		b_clk	: IN STD_LOGIC;
		b_reset_n	: IN STD_LOGIC;
		b1_ena	: IN STD_LOGIC;
		b1_dat	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		b1_sop	: IN STD_LOGIC;
		b1_eop	: IN STD_LOGIC;
		b1_err	: IN STD_LOGIC;
		b1_mty	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		b2_ena	: IN STD_LOGIC;
		b2_dat	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		b2_sop	: IN STD_LOGIC;
		b2_eop	: IN STD_LOGIC;
		b2_err	: IN STD_LOGIC;
		b2_mty	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		a_tenb	: OUT STD_LOGIC;
		a_tsx	: OUT STD_LOGIC;
		a_tdat	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		a_tsop	: OUT STD_LOGIC;
		a_teop	: OUT STD_LOGIC;
		a_terr	: OUT STD_LOGIC;
		a_tmod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		b1_dav	: OUT STD_LOGIC;
		b2_dav	: OUT STD_LOGIC
	);
end component;