link_phy_pl3.cmp

来自「VERILOG五POSPHY LEVEL3电路描述」· CMP 代码 · 共 55 行

-- Generated by POS-PHY Level 2 and 3 Compiler 1.3.1 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

component link_phy_pl3
	PORT (
		a_tfclk	: IN STD_LOGIC;
		a_treset_n	: IN STD_LOGIC;
		a_dtpa	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		b_clk	: IN STD_LOGIC;
		b_reset_n	: IN STD_LOGIC;
		b1_ena	: IN STD_LOGIC;
		b1_dat	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		b1_sop	: IN STD_LOGIC;
		b1_eop	: IN STD_LOGIC;
		b1_err	: IN STD_LOGIC;
		b1_mty	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		b2_ena	: IN STD_LOGIC;
		b2_dat	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		b2_sop	: IN STD_LOGIC;
		b2_eop	: IN STD_LOGIC;
		b2_err	: IN STD_LOGIC;
		b2_mty	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		a_tenb	: OUT STD_LOGIC;
		a_tsx	: OUT STD_LOGIC;
		a_tdat	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		a_tsop	: OUT STD_LOGIC;
		a_teop	: OUT STD_LOGIC;
		a_terr	: OUT STD_LOGIC;
		a_tmod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		b1_dav	: OUT STD_LOGIC;
		b2_dav	: OUT STD_LOGIC
	);
end component;