d_ff2.v

為一個可處理多項式乘法的verilog code

module DFF2(clk,A,B);
input clk;
input A;
output B;
wire s1;
wire Dout;

DFF D1(clk,A,s1);
DFF D2(clk,s1,Dout);
assign B=Dout;
endmodule

module DFF(clk,D,Q);
input clk;
input D;
output Q;
reg Q;

always @(posedge clk)
Q=D;
endmodule