gf_1.v

為一個可處理多項式乘法的verilog code

//****************************main  module***********************************************************************//
module GF_5(D00,D01,D02,D03,D04,A0,A1,A2,A3,A4,B0,B1,B2,B3,B4,C0,C1,C2,C3,C4);
input D00,D01,D02,D03,D04,A0,A1,A2,A3,A4,B0,B1,B2,B3,B4;
output C0,C1,C2,C3,C4;
wire

GF_Cell U00(B0,A0,D00,)



endmodule
//***************************************************************************************************************//


//************************************************GF_cell********************************************************//
module GF_Cell(Xin,Yin,Din,Xout,Yout,Dout,clk);
output Xout,Yout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D1out,D2out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D2(clk,Yin,D2out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Xout=D1out;
assign Yout=D2out;
endmodule
//*******************************************GF_cell   NO   Xout***************************************************************//
module GF_Cell_NX(Xin,Yin,Din,Yout,Dout,clk);
output Yout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D2out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D2(clk,Yin,D2out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Yout=D2out;
endmodule
//*************************************************GF_cell   NO   Yout********************************************************//
module GF_Cell_NY(Xin,Yin,Din,Xout,Dout,clk);
output Xout,Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D1out,D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
assign Xout=D1out;
endmodule
//*************************************************GF_cell   NO  Xout Yout****************************************//
module GF_Cell_NXY(Xin,Yin,Din,Dout,clk);
output Dout;
input  Xin,Yin,Din;
input clk;
wire s1;
wire D3out;

assign s1=(Xin&Yin)^Din;

DFF D1(clk,Xin,D1out);
DFF D3(clk,s1,D3out);

assign Dout=D3out;
endmodule

//*******************************************DFF cell************************************************************//
module DFF(clk,D,Q);
input clk;
input D;
output Q;
reg Q;

always @(posedge clk)
Q=D;
endmodule
//**************************************************************************************************************//