test1.v

為一個可處理多項式乘法的verilog code

module test_DFF;
reg clk;
reg A;
wire B;

DFF2 test(clk,A,B);

initial
clk=0'b0;



initial
$monitor($time,"A=%b,clk=%b",A,clk);

always 
#5 clk=~clk;

initial
begin
  #0 A=1'b0;
  #5 A=1'b0;
  #5 A=1'b1;
  #5 A=1'b0;
  #5 A=1'b0;
  #5 A=1'b1;
  
  
  
end
initial
#100 $stop;
endmodule