display.map.rpt

用 vhdl 语言编写的1602的小程序

Analysis & Synthesis report for DISPLAY
Wed Aug 29 22:51:51 2007
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |DISPLAY|state
  8. State Machine - |DISPLAY|next_command
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Analysis & Synthesis Equations
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
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Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 29 22:51:51 2007         ;
; Quartus II Version          ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name               ; DISPLAY                                       ;
; Top-level Entity Name       ; DISPLAY                                       ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 111                                           ;
; Total pins                  ; 15                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 0                                             ;
; Total PLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


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; Analysis & Synthesis Settings                                                                                ;