display.map.rpt

来自「用 vhdl 语言编写的1602的小程序」· RPT 代码 · 共 302 行 · 第 1/5 页

; next_command.display_off   ; 0                          ; 1                        ; 0                   ; 0                          ; 0                 ; 0                   ; 0                     ; 0                        ; 0                        ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                     ; 0                       ; 0                     ; 1                   ;
; next_command.display_clear ; 1                          ; 0                        ; 0                   ; 0                          ; 0                 ; 0                   ; 0                     ; 0                        ; 0                        ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                         ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                     ; 0                       ; 0                     ; 1                   ;
+----------------------------+----------------------------+--------------------------+---------------------+----------------------------+-------------------+---------------------+-----------------------+--------------------------+--------------------------+---------------------------+---------------------------+---------------------------+---------------------------+---------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+-----------------------+-------------------------+-----------------------+---------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 86    ;
; Number of registers using Synchronous Clear  ; 20    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 65    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; LCD_E~reg0                             ; 2       ;
; DATA_BUS_VALUE[3]                      ; 2       ;
; DATA_BUS_VALUE[4]                      ; 2       ;
; DATA_BUS_VALUE[5]                      ; 2       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |DISPLAY|CLK_COUNT_400HZ[19] ;
; 5:1                ; 34 bits   ; 102 LEs       ; 102 LEs              ; 0 LEs                  ; No         ; |DISPLAY|next_command~87     ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |DISPLAY|Select~10           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/FPGA/DISPLAY/DISPLAY.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Aug 29 22:51:48 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DISPLAY -c DI