adc0809.vhd

VHDL编写的ADC0809 控制器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity adc0809 is
          port(clk,eoc:in std_logic;
                     d:in std_logic_vector(7 downto 0);
                     q:out std_logic_vector(7 downto 0);
  lock1,start,oe,clock:out std_logic;
           add:out std_logic_vector(2 downto 0));
end adc0809;
architecture jiegou of adc0809 is
   type states is(st0,st1,st2,st3,st4,st5);
   signal current_state,next_state:states:=st0;
   signal regl:std_logic_vector(7 downto 0);
   signal lock:std_logic;
   signal clock_a,clock_b:std_logic :='0';
   begin
  add<="000";
  lock1<=lock;
  q<=regl;
clock<=clock_a;
loop1:process(clock_b)
         begin
         if(clock_b'event and clock_b='1')then
              current_state<=next_state;
          end if;
      end process loop1;
loop2:process(lock)
         begin
            if(lock'event and lock='1')then
                regl<=d;
             end if;
       end process loop2;
loop3:process(current_state,eoc)
            begin
             case current_state is
                   when st0 =>start<='0';oe<='0';lock<='0';next_state<=st1;
                   when st1 =>start<='1';oe<='0';lock<='0';next_state<=st2;
                   when st2 =>start<='0';oe<='0';lock<='0';
                              if(eoc='1')then next_state<=st2;
                              else next_state<=st3;
                              end if;
                   when st3 =>start<='0';oe<='0';lock<='0';
                              if(eoc='0')then next_state<=st3;
                              else next_state<=st4;
                              end if;
                   when st4 =>start<='0';oe<='1';lock<='0';
                              next_state<=st5;
                   when st5 =>start<='0';oe<='1';lock<='1';
                              next_state<=st0;
                   when others =>start<='0';oe<='0';lock<='0';next_state<=st0;
             end case;
       end process loop3;
loop4:process(clk)
     variable temp_a:integer range 19 downto 0 :=0;
          begin
           if(clk'event and clk='1')then
                   if(temp_a=19)then temp_a:=0;clock_a<=not clock_a;clock_b<=not clock_b;
                       else
                      temp_a:=temp_a+1;
                   end if;
                    if(temp_a=9)then clock_b<=not clock_b;
                    end if;
           end if;
      end process loop4;
      
end jiegou;