pinlv.vhd

基于单片机与CPLD的 等精度频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pinlv3 is

port(fxclk:in std_logic;
     fsclk:in std_logic;
       clr:in std_logic;
       gate:in std_logic;
       sel:in std_logic_vector(2 downto 0);
     rgate:out std_logic;
      miao:buffer std_logic;
      date:out std_logic_vector(7 downto 0));
end pinlv3;

architecture jiegou of pinlv is
  signal nx,ns:std_logic_vector(31 downto 0);
  signal ena:std_logic;
  begin
    rgate<=ena;
    date<=nx(7 downto 0)when sel="000"
      else nx(15 downto 8)when sel="001"
      else nx(23 downto 16)when sel="010"
      else nx(31 downto 24)when sel="011"
      else ns(7 downto 0)when sel="100"
      else ns(15 downto 8)when sel="101"
      else ns(23 downto 16)when sel="110"
      else ns(31 downto 24)when sel="111"
      else ns(31 downto 24);
count_fx:process(fxclk,clr,ena)
      
            begin
              if(clr='1')then 
                 nx<=(others=>'0');
               elsif(fxclk'event and fxclk='1')then
                    if(ena='1')then
                         nx<=nx+1;
                     end if;
             end if;
      end process count_fx;

count_fs:process(fsclk,clr,ena)
                begin
               if(clr='1')then 
                    ns<=(others=>'0');
                elsif(fsclk'event and fsclk='1')then
                    if(ena='1')then
                         ns<=ns+1;
                     end if;
               end if;
           end process count_fs;
g1:process(clr,fxclk,ena,gate)
 begin
if(clr='1')then
        ena<='0';
 elsif(fxclk'event and fxclk='1')then
        ena<=gate;
 end if;
end process g1;

miao_1:process(fsclk)
variable temp:integer range 19999999 downto 0;
        
     begin
        if(fsclk'event and fsclk='1')then
              if(temp=19999999)then
                   temp:=0;miao<=not miao;
                 else
                   temp:=temp+1;
               end if;
         end if;
     end process miao_1;
end jiegou;