hy57v641620hg.vp.vcs

Hynix公司8M byte sdr sdram的verilog语言仿真实现。

   `define  tAC3max         6  // access time from clock(CL=3)[ns]
   `define  tAC2max         6  // access time from clock(CL=2)[ns]
   `define  tOHmin          3  // data-out hold time[ns]
   `define  tDSmin          2  // data-input setup time[ns]
   `define  tDHmin          1  // data-input hold time[ns]
   `define  tASmin          2  // address setup time[ns]
   `define  tAHmin          1  // address hold time[ns]
   `define  tCKSmin         2  // CKE setup time[ns]
   `define  tCKHmin         1  // CKE hold time[ns]
   `define  tCSmin          2  // command setup time[ns]
   `define  tCHmin          1  // command hold time[ns]
   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]
   `define  tOHZ3min        3  // clock to data output in Hi-Z time(CL=3)[ns]
   `define  tOHZ3max        6  // clock to data output in Hi-Z time(CL=3)[ns]
   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]
   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]
   `define  tRCmin         70  // RAS cycle time @ operation[ns]
   `define  tRFCmin        70  // RAS cycle time @ auto refresh[ns]
   `define  tRCDmin        20  // RAS to CAS delay[ns]
   `define  tRASmin        50  // RAS active time[ns]
   `define  tRASmax    100000  // RAS active time[ns]
   `define  tRPmin         20  // RAS precharge time[ns]
   `define  tRRDmin        20  // RAS to RAS bank active delay[ns]
   `define  tCCDmin         1  // CAS to CAS delay[tCK]
   `define  tWTLmin         0  // write command to data-in delay[tCK]
   `define  tDPLmin         1  // data-in to precharge delay[tCK]
   `define  tDALmin         3  // data-in to active command[tCK]
   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]
   `define  tDQMmin         0  // DQM to data-in mask[tCK]
   `define  tMRDmin         2  // MRS to new command[tCK]
   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]
   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]
   `define  tPDEmin         1  // power down exit time[tCK]
   `define  tSREmin         1  // self refresh exit time[tCK]
   `define  tREFmax  64000000  // refresh time(64ms)[ns]
`endif
 
`ifdef SDR_S
   `define  tCK             6 
   `define  tCK3min        10  // system clock cycle time(CL=3)[ns]
   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]
   `define  tCK2min        12  // system clock cycle time(CL=2)[ns]
   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]
   `define  tCHWmin         3  // clock high pulse width[ns]
   `define  tCLWmin         3  // clock low pulse width[ns]
   `define  tAC3max         6  // access time from clock(CL=3)[ns]
   `define  tAC2max         6  // access time from clock(CL=2)[ns]
   `define  tOHmin          3  // data-out hold time[ns]
   `define  tDSmin          2  // data-input setup time[ns]
   `define  tDHmin          1  // data-input hold time[ns]
   `define  tASmin          2  // address setup time[ns]
   `define  tAHmin          1  // address hold time[ns]
   `define  tCKSmin         2  // CKE setup time[ns]
   `define  tCKHmin         1  // CKE hold time[ns]
   `define  tCSmin          2  // command setup time[ns]
   `define  tCHmin          1  // command hold time[ns]
   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]
   `define  tOHZ3min        3  // clock to data output in Hi-Z time(CL=3)[ns]
   `define  tOHZ3max        6  // clock to data output in Hi-Z time(CL=3)[ns]
   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]
   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]
   `define  tRCmin         70  // RAS cycle time @ operation[ns]
   `define  tRFCmin        70  // RAS cycle time @ auto refresh[ns]
   `define  tRCDmin        20  // RAS to CAS delay[ns]
   `define  tRASmin        50  // RAS active time[ns]
   `define  tRASmax    100000  // RAS active time[ns]
   `define  tRPmin         20  // RAS precharge time[ns]
   `define  tRRDmin        20  // RAS to RAS bank active delay[ns]
   `define  tCCDmin         1  // CAS to CAS delay[tCK]
   `define  tWTLmin         0  // write command to data-in delay[tCK]
   `define  tDPLmin         1  // data-in to precharge delay[tCK]
   `define  tDALmin         3  // data-in to active command[tCK]
   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]
   `define  tDQMmin         0  // DQM to data-in mask[tCK]
   `define  tMRDmin         2  // MRS to new command[tCK]
   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]
   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]
   `define  tPDEmin         1  // power down exit time[tCK]
   `define  tSREmin         1  // self refresh exit time[tCK]
   `define  tREFmax  64000000  // refresh time(64ms)[ns]
`endif
 
`ifdef SDR64Mx4
   `define  data_bits        4 // number of data bit
   `define  addr_bits       12 // number of external address bit
   `define  col_bits        10 // number of column address bit
   `define  bank_size  4194304 // bank depth : 2^(addr_bits + col_bits)
   `define  HiZ           4'bz

   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);
   input                  dqm;
`endif

`ifdef SDR64Mx8
   `define  data_bits        8 // number of data bit
   `define  addr_bits       12 // number of external address bit
   `define  col_bits         9 // number of column address bit
   `define  bank_size  2097152 // bank depth : 2^(addr_bits + col_bits)
   `define  HiZ           8'bz

   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);
   input                  dqm;
`endif

`ifdef SDR64Mx16
   `define  data_bits       16 // number of data bit
   `define  addr_bits       12 // number of external address bit
   `define  col_bits         8 // number of column address bit
   `define  bank_size  1048576 // bank depth : 2^(addr_bits + col_bits)
   `define  HiZ          16'bz

   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, udqm, ldqm);
   input                  udqm;
   input                  ldqm;
`endif

input                  clk;
input                  cke;
input                  cs_n;
input                  ras_n;
input                  cas_n;
input                  we_n;
input            [1:0] ba;
input [`addr_bits-1:0] addr;
inout [`data_bits-1:0] dq;

`ifdef VCS  // VCS Release 6.0
`protected
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