mul2.vhd

用VHDL编写的计算器

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:29:19 11/16/2006 
-- Design Name: 
-- Module Name:    shiftl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul2 is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (8 downto 0);
         --  start : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           num : out  STD_LOGIC_VECTOR (11 downto 0));
end mul2;

architecture Behavioral of mul2 is

begin


process(clk,num1,num2)
variable acc:std_logic_vector(11 downto 0);
variable q:std_logic_vector(11 downto 0);
variable ma:std_logic_vector(11 downto 0);
begin
  if rising_edge(clk)then
  ma:="00000000"&num1;
  acc:="000000000000";
  for i in 0 to 8 loop
     for j in  0 to 11 loop
	  q(j):=num2(i)and ma(j);
	  end loop;
	  acc:=acc+q;
	  ma:=ma(10 downto 0)&ma(11);
	end loop;
	num<=acc;
	end if;
end process;
  

end Behavioral;