add1.vhd

用VHDL编写的计算器

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:59:47 11/09/2006 
-- Design Name: 
-- Module Name:    add - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add1 is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out STD_LOGIC
			 );
end add1;

architecture Behavioral of add1 is
component fadd4 is
port(
  	a	: in std_logic_vector(3 downto 0);
	b 	: in std_logic_vector(3 downto 0);
  	ci 	: in std_logic;
  	co 	: out std_logic;
  	sum : out std_logic_vector(3 downto 0));
end component;
signal sum,ct,sum1:std_logic_vector(3 downto 0);

signal ci,co,cnons:std_logic;
signal t:std_logic;
begin
ci<='0';num(3 downto 0)<=sum1;cout<=t;
t<=co or(sum(3)and sum(2)) or (sum(3) and sum(1));
ct<='0'&t&t&'0';
u1:fadd4 port map(num1,num2,ci,co,sum);
u2:fadd4 port map(sum,ct,ci,cnons,sum1);
process(t)
begin
--if rising_edge(clk)then
   if t='1' then
	num(7 downto 4)<="0001";
	else
	num(7 downto 4)<="0000";
   end if;
--end if;
end process;

end Behavioral;