cordic_par_seq_apb.v

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// CORDIC_par_seq_APB.v   Core ALU of a CORDIC rotator,
//                        word-sequential implementation
//                        with APB interface
// Doulos Ltd.
//
// Revision information:
// 0.0  19-Jan-2004   Jonathan Bromley
//   Modified from CORDIC_par_seq_tci.v
//
// -------
// PURPOSE
// -------
//
// APB bus interface wrapper for CORDIC rotator
//

// This is a synthesisable design and doesn't need a `timescale,
// but we include one here to avoid any dependence on compilation order.
//
`timescale 1ns/1ns
`default_nettype none


//_________________________________________ module CORDIC_par_seq_APB ___

module CORDIC_par_seq_APB
    #( parameter
         baseAddress = 16'hFE00,
         slave_Tco   = 2
     )
    (
      APB.RTL_slave bus,
      input async_reset
    );


  localparam

    data_X = {$bits(T_sdata){1'bx}},

    reg_sel_bits = 2,
    adr_cmd    = 0,
    adr_status = 0,
    adr_angle  = 1,
    adr_x      = 2,
    adr_y      = 3;

  struct packed {
    logic [15:2] junk;
    logic interrupted;
    logic busy;
  } status_word;

  T_sdata    angleIn;
  T_sdata   xIn, yIn;

  T_sdata   angleOut;
  T_sdata xOut, yOut;

  logic [reg_sel_bits-1:0] reg_select;

  // The PSEL signal really comes from the APB bus, but because of modport
  // limitations we need to generate it locally...
  logic PSEL;

  logic start, busy, interrupted;

  assign PSEL = bus.psel &&
              ((baseAddress >> reg_sel_bits) == (bus.PADDR >> reg_sel_bits));

  assign reg_select = bus.PADDR[reg_sel_bits-1:0];

  assign status_word = { {14'b0}, {interrupted}, {busy} };
                       // .junk   .interrupted   .busy

  always @(posedge bus.PCLK or posedge async_reset) begin : BusStateMachine

    if (async_reset) begin

      interrupted <= 0;
      angleIn     <= 0;
      xIn         <= 0;
      yIn         <= 0;
      start       <= 0;

    end else begin  // Clocked logic

      // start signal persists only for one clock.
      start <= 0;

      if (PSEL) begin  // It's a bus cycle for us

        if (bus.PWRITE) begin   // We're in our own data write cycle

          if (!bus.PENABLE) begin // Write data on setup cycle
            case (reg_select)
              adr_cmd: // Initiate command, capture "interrupted" status
                 begin
                   interrupted <= busy;
                   start <= 1;
                 end
              adr_angle: // Write to angle register
                 begin
                   angleIn <= bus.PWDATA;
                 end
              adr_x: // Write to X register
                 begin
                   xIn <= bus.PWDATA;
                 end
              adr_y: // Write to Y register
                 begin
                   yIn <= bus.PWDATA;
                 end
            endcase
          end // if (bus.PENABLE)

        end else if (!bus.PWRITE) begin // Read cycle

          if (!bus.PENABLE) begin  // Set up read data on setup phase
            case (reg_select)
              adr_status: bus.PRDATA <= #slave_Tco status_word;
              adr_angle : bus.PRDATA <= #slave_Tco angleOut;
              adr_x     : bus.PRDATA <= #slave_Tco xOut;
              adr_y     : bus.PRDATA <= #slave_Tco yOut;
              default   : bus.PRDATA <= #slave_Tco data_X;
            endcase
          end // if (!bus.PENABLE)

        end  // if (bus.PWRITE)... else ...

      end // if (PSEL)...

    end // if (async_reset)... else [clocked logic]

  end // BusStateMachine


  CORDIC_par_seq #(
      .guardBits(3),
      .stepBits(4)
     )
    processor (
      .reduceNotRotate(bus.PWDATA[0]),
      .clock(bus.PCLK),
      .reset(async_reset),
      .*
    );  // processor


endmodule // CORDIC_par_seq_APB

// _______________________________________________________________________