📄 dds.sim.rpt
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; |DDS|REG32B:U3|Dout[30]~76 ; |DDS|REG32B:U3|Dout[30]~90 ; cout ;
; |DDS|REG32B:U3|Dout[31]~77 ; |DDS|REG32B:U3|Dout[31]~77 ; combout ;
; |DDS|clk ; |DDS|clk ; combout ;
; |DDS|Fout[0] ; |DDS|Fout[0] ; padio ;
; |DDS|Fout[1] ; |DDS|Fout[1] ; padio ;
; |DDS|Fout[2] ; |DDS|Fout[2] ; padio ;
; |DDS|Fout[3] ; |DDS|Fout[3] ; padio ;
; |DDS|Fout[4] ; |DDS|Fout[4] ; padio ;
; |DDS|Fout[5] ; |DDS|Fout[5] ; padio ;
; |DDS|Fout[6] ; |DDS|Fout[6] ; padio ;
; |DDS|Fout[7] ; |DDS|Fout[7] ; padio ;
; |DDS|Fout[8] ; |DDS|Fout[8] ; padio ;
; |DDS|Fout[9] ; |DDS|Fout[9] ; padio ;
; |DDS|clk~clkctrl ; |DDS|clk~clkctrl ; outclk ;
; |DDS|REG10B:U5|Dout[0]~feeder ; |DDS|REG10B:U5|Dout[0]~feeder ; combout ;
; |DDS|REG10B:U5|Dout[1]~feeder ; |DDS|REG10B:U5|Dout[1]~feeder ; combout ;
+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[0] ; portbdataout0 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[5] ; portbdataout1 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[7] ; portbdataout2 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[9] ; portbdataout3 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[1] ; portbdataout0 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[2] ; portbdataout1 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[4] ; portbdataout2 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[8] ; portbdataout3 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[3] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[3] ; portbdataout0 ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[3] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_b[6] ; portbdataout1 ;
; |DDS|altera_internal_jtag~TDO ; |DDS|altera_internal_jtag~TDO ; tdo ;
; |DDS|altera_internal_jtag~TDO ; |DDS|altera_internal_jtag~TMSUTAP ; tmsutap ;
; |DDS|altera_internal_jtag~TDO ; |DDS|altera_internal_jtag~TCKUTAP ; tckutap ;
; |DDS|altera_internal_jtag~TDO ; |DDS|altera_internal_jtag ; tdiutap ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] ; regout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode_usr1 ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode_usr1 ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 ; combout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 ; combout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] ; regout ;
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