dds.sim.rpt
来自「基于FPGA平台」· RPT 代码 · 共 299 行 · 第 1/5 页
RPT
299 行
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[8] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[8] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[9] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[9] ; regout ;
; |DDS|sld_hub:sld_hub_inst|hub_tdo ; |DDS|sld_hub:sld_hub_inst|hub_tdo ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~14 ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~14 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|IRF_D[1][2]~45 ; |DDS|sld_hub:sld_hub_inst|IRF_D[1][2]~45 ; combout ;
; |DDS|sld_hub:sld_hub_inst|CLR_SIGNAL ; |DDS|sld_hub:sld_hub_inst|CLR_SIGNAL ; regout ;
; |DDS|sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q ; |DDS|sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q ; regout ;
; |DDS|sld_hub:sld_hub_inst|GEN_SHADOW_IRF~9 ; |DDS|sld_hub:sld_hub_inst|GEN_SHADOW_IRF~9 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[2] ; |DDS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|IRF_ENABLE[1]~64 ; |DDS|sld_hub:sld_hub_inst|IRF_ENABLE[1]~64 ; combout ;
; |DDS|sld_hub:sld_hub_inst|IRF_ENABLE[1]~65 ; |DDS|sld_hub:sld_hub_inst|IRF_ENABLE[1]~65 ; combout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode_usr0 ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode_usr0 ; regout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~2 ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~2 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~171 ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~171 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] ; regout ;
; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~172 ; |DDS|sld_hub:sld_hub_inst|jtag_debug_mode~172 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] ; regout ;
; |DDS|sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 ; |DDS|sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 ; combout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] ; regout ;
; |DDS|sld_hub:sld_hub_inst|Equal0~83 ; |DDS|sld_hub:sld_hub_inst|Equal0~83 ; combout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] ; regout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] ; regout ;
; |DDS|sld_hub:sld_hub_inst|Equal0~84 ; |DDS|sld_hub:sld_hub_inst|Equal0~84 ; combout ;
; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] ; |DDS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] ; regout ;
; |DDS|sld_hub:sld_hub_inst|Equal1~29 ; |DDS|sld_hub:sld_hub_inst|Equal1~29 ; combout ;
; |DDS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[1] ; |DDS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[1] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~52 ; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~52 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] ; |DDS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~59 ; |DDS|sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~59 ; combout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~53 ; |DDS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~53 ; combout ;
; |DDS|REG10B:U5|Dout[2]~42 ; |DDS|REG10B:U5|Dout[2]~50 ; cout ;
; |DDS|REG10B:U5|Dout[3]~43 ; |DDS|REG10B:U5|Dout[3]~51 ; cout ;
; |DDS|REG10B:U5|Dout[4]~44 ; |DDS|REG10B:U5|Dout[4]~52 ; cout ;
; |DDS|REG10B:U5|Dout[5]~45 ; |DDS|REG10B:U5|Dout[5]~53 ; cout ;
; |DDS|REG10B:U5|Dout[6]~46 ; |DDS|REG10B:U5|Dout[6]~54 ; cout ;
; |DDS|REG10B:U5|Dout[7]~47 ; |DDS|REG10B:U5|Dout[7]~55 ; cout ;
; |DDS|REG10B:U5|Dout[8]~48 ; |DDS|REG10B:U5|Dout[8]~56 ; cout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] ; regout ;
; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] ; |DDS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; regout ;
; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ; |DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|
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