ddsok.tan.rpt

来自「DDS信号发生器」· RPT 代码 · 共 178 行 · 第 1/5 页

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                  ; To                                                                                                                                                                                        ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 8.124 ns                         ; fword[6]                                                                                                                                                              ; adderful1:u1|add32:u0|s[31]                                                                                                                                                               ; --                           ; clok                         ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 10.086 ns                        ; data_rom:u2|altsyncram:altsyncram_component|altsyncram_cs41:auto_generated|altsyncram_ani2:altsyncram1|q_a[0]                                                         ; fout[0]                                                                                                                                                                                   ; clok                         ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                              ; altera_reserved_tdo                                                                                                                                                                       ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.588 ns                         ; altera_internal_jtag                                                                                                                                                  ; sld_signaltap:cnts|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[47] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 124.19 MHz ( period = 8.052 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3]                                                                                                                    ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                              ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clok'                         ; N/A   ; None          ; 158.96 MHz ( period = 6.291 ns ) ; sld_signaltap:cnts|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] ; sld_signaltap:cnts|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[5]                     ; clok                         ; clok                         ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                       ;                                                                                                                                                                                           ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;