data_rom.tan.qmsg

DDS信号发生器

{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5 address\[5\] clock 3.406 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5\" (data pin = \"address\[5\]\", clock pin = \"clock\") is 3.406 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.260 ns + Longest pin memory " "Info: + Longest pin to memory delay is 6.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns address\[5\] 1 PIN PIN_E14 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_E14; Fanout = 2; PIN Node = 'address\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { address[5] } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.920 ns) + CELL(0.253 ns) 6.260 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5 2 MEM M4K_X15_Y14 4 " "Info: 2: + IC(4.920 ns) + CELL(0.253 ns) = 6.260 ns; Loc. = M4K_X15_Y14; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.173 ns" { address[5] altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 21.41 % ) " "Info: Total cell delay = 1.340 ns ( 21.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.920 ns ( 78.59 % ) " "Info: Total interconnect delay = 4.920 ns ( 78.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.260 ns" { address[5] altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.260 ns" { address[5] address[5]~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } { 0.000ns 0.000ns 4.920ns } { 0.000ns 1.087ns 0.253ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" {  } { { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.985 ns - Shortest memory " "Info: - Shortest clock path from clock \"clock\" to destination memory is 2.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 46 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 46; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(0.512 ns) 2.985 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5 2 MEM M4K_X15_Y14 4 " "Info: 2: + IC(1.645 ns) + CELL(0.512 ns) = 2.985 ns; Loc. = M4K_X15_Y14; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.157 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 44.89 % ) " "Info: Total cell delay = 1.340 ns ( 44.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.645 ns ( 55.11 % ) " "Info: Total interconnect delay = 1.645 ns ( 55.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.985 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.985 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.260 ns" { address[5] altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.260 ns" { address[5] address[5]~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } { 0.000ns 0.000ns 4.920ns } { 0.000ns 1.087ns 0.253ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.985 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.985 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[0\] altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 7.684 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[0\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]\" is 7.684 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.973 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 46 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 46; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(0.500 ns) 2.973 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 2 MEM M4K_X15_Y14 1 " "Info: 2: + IC(1.645 ns) + CELL(0.500 ns) = 2.973 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.145 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 44.67 % ) " "Info: Total cell delay = 1.328 ns ( 44.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.645 ns ( 55.33 % ) " "Info: Total interconnect delay = 1.645 ns ( 55.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.973 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.973 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.500ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.291 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 1 MEM M4K_X15_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.816 ns) + CELL(2.404 ns) 4.291 ns q\[0\] 2 PIN PIN_U15 0 " "Info: 2: + IC(1.816 ns) + CELL(2.404 ns) = 4.291 ns; Loc. = PIN_U15; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.220 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] q[0] } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.475 ns ( 57.68 % ) " "Info: Total cell delay = 2.475 ns ( 57.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.816 ns ( 42.32 % ) " "Info: Total interconnect delay = 1.816 ns ( 42.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.291 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.291 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] q[0] } { 0.000ns 1.816ns } { 0.071ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.973 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.973 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.500ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.291 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.291 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] q[0] } { 0.000ns 1.816ns } { 0.071ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.404 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN ELA_X0_Y15_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.404 ns) 2.404 ns altera_reserved_tdo 2 PIN PIN_H11 0 " "Info: 2: + IC(0.000 ns) + CELL(2.404 ns) = 2.404 ns; Loc. = PIN_H11; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 100.00 % ) " "Info: Total cell delay = 2.404 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}