data_rom.tan.qmsg

DDS信号发生器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 43 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0 memory altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 290.87 MHz 3.438 ns Internal " "Info: Clock \"clock\" has Internal fmax of 290.87 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]\" (period= 3.438 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.875 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X15_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y14; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.875 ns) 2.875 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 2 MEM M4K_X15_Y14 1 " "Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.875 ns ( 100.00 % ) " "Info: Total cell delay = 2.875 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.973 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 46 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 46; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(0.500 ns) 2.973 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\] 2 MEM M4K_X15_Y14 1 " "Info: 2: + IC(1.645 ns) + CELL(0.500 ns) = 2.973 ns; Loc. = M4K_X15_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.145 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 44.67 % ) " "Info: Total cell delay = 1.328 ns ( 44.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.645 ns ( 55.33 % ) " "Info: Total interconnect delay = 1.645 ns ( 55.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.973 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.973 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.500ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.985 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_M20 46 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 46; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "data_rom.vhd" "" { Text "D:/altera/quartus60/program/DDS/data_rom.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.645 ns) + CELL(0.512 ns) 2.985 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X15_Y14 4 " "Info: 2: + IC(1.645 ns) + CELL(0.512 ns) = 2.985 ns; Loc. = M4K_X15_Y14; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|altsyncram_7oi2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.157 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns ( 44.89 % ) " "Info: Total cell delay = 1.340 ns ( 44.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.645 ns ( 55.11 % ) " "Info: Total interconnect delay = 1.645 ns ( 55.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.985 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.985 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.973 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.973 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.500ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.985 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.985 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" {  } { { "db/altsyncram_7oi2.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/altsyncram_7oi2.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.973 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.973 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.500ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.985 ns" { clock altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.985 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 1.645ns } { 0.000ns 0.828ns 0.512ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\] register sld_hub:sld_hub_inst\|hub_tdo 189.39 MHz 5.28 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 189.39 MHz between source register \"sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 5.28 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.444 ns + Longest register register " "Info: + Longest register to register delay is 2.444 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\] 1 REG LC_X14_Y13_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y13_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "db/decode_lhi.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/decode_lhi.tdf" 32 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.280 ns) 1.206 ns sld_hub:sld_hub_inst\|hub_tdo~564 2 COMB LC_X18_Y13_N0 1 " "Info: 2: + IC(0.926 ns) + CELL(0.280 ns) = 1.206 ns; Loc. = LC_X18_Y13_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~564'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.206 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo~564 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.366 ns) 2.087 ns sld_hub:sld_hub_inst\|hub_tdo~565 3 COMB LC_X18_Y13_N8 1 " "Info: 3: + IC(0.515 ns) + CELL(0.366 ns) = 2.087 ns; Loc. = LC_X18_Y13_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~565'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.881 ns" { sld_hub:sld_hub_inst|hub_tdo~564 sld_hub:sld_hub_inst|hub_tdo~565 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 2.444 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X18_Y13_N9 1 " "Info: 4: + IC(0.134 ns) + CELL(0.223 ns) = 2.444 ns; Loc. = LC_X18_Y13_N9; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.357 ns" { sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.869 ns ( 35.56 % ) " "Info: Total cell delay = 0.869 ns ( 35.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.575 ns ( 64.44 % ) " "Info: Total interconnect delay = 1.575 ns ( 64.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.444 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo~564 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.444 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo~564 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.926ns 0.515ns 0.134ns } { 0.000ns 0.280ns 0.366ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.030 ns - Smallest " "Info: - Smallest clock skew is -0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.731 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK ELA_X0_Y15_N0 145 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 145; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.189 ns) + CELL(0.542 ns) 3.731 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X18_Y13_N9 1 " "Info: 2: + IC(3.189 ns) + CELL(0.542 ns) = 3.731 ns; Loc. = LC_X18_Y13_N9; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns ( 14.53 % ) " "Info: Total cell delay = 0.542 ns ( 14.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.189 ns ( 85.47 % ) " "Info: Total interconnect delay = 3.189 ns ( 85.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.189ns } { 0.000ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 3.761 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 3.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK ELA_X0_Y15_N0 145 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 145; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.219 ns) + CELL(0.542 ns) 3.761 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\] 2 REG LC_X14_Y13_N5 1 " "Info: 2: + IC(3.219 ns) + CELL(0.542 ns) = 3.761 ns; Loc. = LC_X14_Y13_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_lhi:auto_generated\|dffe1a\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "db/decode_lhi.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/decode_lhi.tdf" 32 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns ( 14.41 % ) " "Info: Total cell delay = 0.542 ns ( 14.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.219 ns ( 85.59 % ) " "Info: Total interconnect delay = 3.219 ns ( 85.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } { 0.000ns 3.219ns } { 0.000ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.189ns } { 0.000ns 0.542ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } { 0.000ns 3.219ns } { 0.000ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/decode_lhi.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/decode_lhi.tdf" 32 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "db/decode_lhi.tdf" "" { Text "D:/altera/quartus60/program/DDS/db/decode_lhi.tdf" 32 8 0 } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.444 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo~564 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.444 ns" { sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] sld_hub:sld_hub_inst|hub_tdo~564 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.926ns 0.515ns 0.134ns } { 0.000ns 0.280ns 0.366ns 0.223ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.731 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.189ns } { 0.000ns 0.542ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.761 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] } { 0.000ns 3.219ns } { 0.000ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}