data_rom.fit.qmsg

DDS信号发生器

{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.652 ns register register " "Info: Estimated most critical path is register to register delay of 4.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LAB_X19_Y14 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y14; Fanout = 16; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.183 ns) 1.382 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|name_gen~33 2 COMB LAB_X17_Y13 8 " "Info: 2: + IC(1.199 ns) + CELL(0.183 ns) = 1.382 ns; Loc. = LAB_X17_Y13; Fanout = 8; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|name_gen~33'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.382 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.075 ns) 2.485 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr 3 COMB LAB_X18_Y15 3 " "Info: 3: + IC(1.028 ns) + CELL(0.075 ns) = 2.485 ns; Loc. = LAB_X18_Y15; Fanout = 3; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.103 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.344 ns) 3.666 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~120 4 COMB LAB_X14_Y15 2 " "Info: 4: + IC(0.837 ns) + CELL(0.344 ns) = 3.666 ns; Loc. = LAB_X14_Y15; Fanout = 2; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~120'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.181 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~120 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 3.724 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~121 5 COMB LAB_X14_Y15 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 3.724 ns; Loc. = LAB_X14_Y15; Fanout = 2; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~121'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~120 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~121 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 3.782 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~122 6 COMB LAB_X14_Y15 2 " "Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 3.782 ns; Loc. = LAB_X14_Y15; Fanout = 2; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~122'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~121 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~122 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 3.840 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~123 7 COMB LAB_X14_Y15 2 " "Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 3.840 ns; Loc. = LAB_X14_Y15; Fanout = 2; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~123'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~122 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~123 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 4.054 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~124 8 COMB LAB_X14_Y15 5 " "Info: 8: + IC(0.000 ns) + CELL(0.214 ns) = 4.054 ns; Loc. = LAB_X14_Y15; Fanout = 5; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~124'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.214 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~123 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~124 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.598 ns) 4.652 ns altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] 9 REG LAB_X14_Y15 12 " "Info: 9: + IC(0.000 ns) + CELL(0.598 ns) = 4.652 ns; Loc. = LAB_X14_Y15; Fanout = 12; REG Node = 'altsyncram:altsyncram_component\|altsyncram_9t41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.598 ns" { altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~124 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.588 ns ( 34.14 % ) " "Info: Total cell delay = 1.588 ns ( 34.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.064 ns ( 65.86 % ) " "Info: Total interconnect delay = 3.064 ns ( 65.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.652 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~120 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~121 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~122 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~123 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~124 altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x10_y10 x20_y20 " "Info: The peak interconnect region extends from location x10_y10 to location x20_y20" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}