adderful1.tan.qmsg

DDS信号发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register add32:u0\|s\[22\] register add32:u0\|s\[16\] 207.13 MHz 4.828 ns Internal " "Info: Clock \"clock\" has Internal fmax of 207.13 MHz between source register \"add32:u0\|s\[22\]\" and destination register \"add32:u0\|s\[16\]\" (period= 4.828 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.567 ns + Longest register register " "Info: + Longest register to register delay is 4.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add32:u0\|s\[22\] 1 REG LC_X4_Y7_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y7_N6; Fanout = 5; REG Node = 'add32:u0\|s\[22\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { add32:u0|s[22] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.590 ns) 1.861 ns add32:u0\|LessThan0~311 2 COMB LC_X4_Y6_N7 1 " "Info: 2: + IC(1.271 ns) + CELL(0.590 ns) = 1.861 ns; Loc. = LC_X4_Y6_N7; Fanout = 1; COMB Node = 'add32:u0\|LessThan0~311'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.861 ns" { add32:u0|s[22] add32:u0|LessThan0~311 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.157 ns add32:u0\|LessThan0~313 3 COMB LC_X4_Y6_N8 32 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.157 ns; Loc. = LC_X4_Y6_N8; Fanout = 32; COMB Node = 'add32:u0\|LessThan0~313'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { add32:u0|LessThan0~311 add32:u0|LessThan0~313 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(1.112 ns) 4.567 ns add32:u0\|s\[16\] 4 REG LC_X4_Y7_N0 4 " "Info: 4: + IC(1.298 ns) + CELL(1.112 ns) = 4.567 ns; Loc. = LC_X4_Y7_N0; Fanout = 4; REG Node = 'add32:u0\|s\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.410 ns" { add32:u0|LessThan0~313 add32:u0|s[16] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 39.76 % ) " "Info: Total cell delay = 1.816 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.751 ns ( 60.24 % ) " "Info: Total interconnect delay = 2.751 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.567 ns" { add32:u0|s[22] add32:u0|LessThan0~311 add32:u0|LessThan0~313 add32:u0|s[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.567 ns" { add32:u0|s[22] add32:u0|LessThan0~311 add32:u0|LessThan0~313 add32:u0|s[16] } { 0.000ns 1.271ns 0.182ns 1.298ns } { 0.000ns 0.590ns 0.114ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.170 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 64; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns add32:u0\|s\[16\] 2 REG LC_X4_Y7_N0 4 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X4_Y7_N0; Fanout = 4; REG Node = 'add32:u0\|s\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clock add32:u0|s[16] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[16] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.170 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 64; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns add32:u0\|s\[22\] 2 REG LC_X4_Y7_N6 5 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X4_Y7_N6; Fanout = 5; REG Node = 'add32:u0\|s\[22\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clock add32:u0|s[22] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[22] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[16] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[22] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.567 ns" { add32:u0|s[22] add32:u0|LessThan0~311 add32:u0|LessThan0~313 add32:u0|s[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.567 ns" { add32:u0|s[22] add32:u0|LessThan0~311 add32:u0|LessThan0~313 add32:u0|s[16] } { 0.000ns 1.271ns 0.182ns 1.298ns } { 0.000ns 0.590ns 0.114ns 1.112ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[16] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[22] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[22] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "add32:u0\|s\[31\] pk\[20\] clock 8.019 ns register " "Info: tsu for register \"add32:u0\|s\[31\]\" (data pin = \"pk\[20\]\", clock pin = \"clock\") is 8.019 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.152 ns + Longest pin register " "Info: + Longest pin to register delay is 11.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns pk\[20\] 1 PIN PIN_215 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_215; Fanout = 2; PIN Node = 'pk\[20\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pk[20] } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.776 ns) + CELL(0.718 ns) 9.969 ns add32:u0\|s\[20\]~334 2 COMB LC_X4_Y7_N4 6 " "Info: 2: + IC(7.776 ns) + CELL(0.718 ns) = 9.969 ns; Loc. = LC_X4_Y7_N4; Fanout = 6; COMB Node = 'add32:u0\|s\[20\]~334'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.494 ns" { pk[20] add32:u0|s[20]~334 } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 10.177 ns add32:u0\|s\[25\]~339 3 COMB LC_X4_Y7_N9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.208 ns) = 10.177 ns; Loc. = LC_X4_Y7_N9; Fanout = 6; COMB Node = 'add32:u0\|s\[25\]~339'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { add32:u0|s[20]~334 add32:u0|s[25]~339 } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.313 ns add32:u0\|s\[30\]~344 4 COMB LC_X4_Y6_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.136 ns) = 10.313 ns; Loc. = LC_X4_Y6_N4; Fanout = 1; COMB Node = 'add32:u0\|s\[30\]~344'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { add32:u0|s[25]~339 add32:u0|s[30]~344 } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.152 ns add32:u0\|s\[31\] 5 REG LC_X4_Y6_N5 3 " "Info: 5: + IC(0.000 ns) + CELL(0.839 ns) = 11.152 ns; Loc. = LC_X4_Y6_N5; Fanout = 3; REG Node = 'add32:u0\|s\[31\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { add32:u0|s[30]~344 add32:u0|s[31] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.376 ns ( 30.27 % ) " "Info: Total cell delay = 3.376 ns ( 30.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.776 ns ( 69.73 % ) " "Info: Total interconnect delay = 7.776 ns ( 69.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.152 ns" { pk[20] add32:u0|s[20]~334 add32:u0|s[25]~339 add32:u0|s[30]~344 add32:u0|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.152 ns" { pk[20] pk[20]~out0 add32:u0|s[20]~334 add32:u0|s[25]~339 add32:u0|s[30]~344 add32:u0|s[31] } { 0.000ns 0.000ns 7.776ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.718ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 64; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns add32:u0\|s\[31\] 2 REG LC_X4_Y6_N5 3 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X4_Y6_N5; Fanout = 3; REG Node = 'add32:u0\|s\[31\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clock add32:u0|s[31] } "NODE_NAME" } } { "add32.vhd" "" { Text "D:/altera/quartus60/program/DDS/add32.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[31] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.152 ns" { pk[20] add32:u0|s[20]~334 add32:u0|s[25]~339 add32:u0|s[30]~344 add32:u0|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.152 ns" { pk[20] pk[20]~out0 add32:u0|s[20]~334 add32:u0|s[25]~339 add32:u0|s[30]~344 add32:u0|s[31] } { 0.000ns 0.000ns 7.776ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.718ns 0.208ns 0.136ns 0.839ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock add32:u0|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 add32:u0|s[31] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock qk\[31\] adderful:u1\|s\[31\] 9.343 ns register " "Info: tco from clock \"clock\" to destination pin \"qk\[31\]\" through register \"adderful:u1\|s\[31\]\" is 9.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 64; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns adderful:u1\|s\[31\] 2 REG LC_X4_Y6_N6 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X4_Y6_N6; Fanout = 1; REG Node = 'adderful:u1\|s\[31\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clock adderful:u1|s[31] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock adderful:u1|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 adderful:u1|s[31] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.949 ns + Longest register pin " "Info: + Longest register to pin delay is 5.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adderful:u1\|s\[31\] 1 REG LC_X4_Y6_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y6_N6; Fanout = 1; REG Node = 'adderful:u1\|s\[31\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adderful:u1|s[31] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.841 ns) + CELL(2.108 ns) 5.949 ns qk\[31\] 2 PIN PIN_228 0 " "Info: 2: + IC(3.841 ns) + CELL(2.108 ns) = 5.949 ns; Loc. = PIN_228; Fanout = 0; PIN Node = 'qk\[31\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.949 ns" { adderful:u1|s[31] qk[31] } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 35.43 % ) " "Info: Total cell delay = 2.108 ns ( 35.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.841 ns ( 64.57 % ) " "Info: Total interconnect delay = 3.841 ns ( 64.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.949 ns" { adderful:u1|s[31] qk[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.949 ns" { adderful:u1|s[31] qk[31] } { 0.000ns 3.841ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock adderful:u1|s[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 adderful:u1|s[31] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.949 ns" { adderful:u1|s[31] qk[31] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.949 ns" { adderful:u1|s[31] qk[31] } { 0.000ns 3.841ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "adderful:u1\|s\[30\] wk\[1\] clock -3.999 ns register " "Info: th for register \"adderful:u1\|s\[30\]\" (data pin = \"wk\[1\]\", clock pin = \"clock\") is -3.999 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 64; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns adderful:u1\|s\[30\] 2 REG LC_X2_Y6_N2 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X2_Y6_N2; Fanout = 1; REG Node = 'adderful:u1\|s\[30\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clock adderful:u1|s[30] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock adderful:u1|s[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 adderful:u1|s[30] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.184 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wk\[1\] 1 PIN PIN_49 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_49; Fanout = 2; PIN Node = 'wk\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wk[1] } "NODE_NAME" } } { "adderful1.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.406 ns) + CELL(0.309 ns) 7.184 ns adderful:u1\|s\[30\] 2 REG LC_X2_Y6_N2 1 " "Info: 2: + IC(5.406 ns) + CELL(0.309 ns) = 7.184 ns; Loc. = LC_X2_Y6_N2; Fanout = 1; REG Node = 'adderful:u1\|s\[30\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.715 ns" { wk[1] adderful:u1|s[30] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 24.75 % ) " "Info: Total cell delay = 1.778 ns ( 24.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.406 ns ( 75.25 % ) " "Info: Total interconnect delay = 5.406 ns ( 75.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.184 ns" { wk[1] adderful:u1|s[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.184 ns" { wk[1] wk[1]~out0 adderful:u1|s[30] } { 0.000ns 0.000ns 5.406ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clock adderful:u1|s[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clock clock~out0 adderful:u1|s[30] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.184 ns" { wk[1] adderful:u1|s[30] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.184 ns" { wk[1] wk[1]~out0 adderful:u1|s[30] } { 0.000ns 0.000ns 5.406ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}