adderful.vhd

DDS信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adderful is
  port( clk:in std_logic;
        wp:in  std_logic_vector(1 downto 0);
        p :in std_logic_vector(31 downto 0);
         q:out std_logic_vector(31 downto 0)
     );
 end adderful;
architecture rets of adderful is
signal s:std_logic_vector(31 downto 0);
begin
 process(clk,wp)
  variable h,g:std_logic_vector(31 downto 0);
  begin
    h:="01000000000000000000000000000000";
    g:="10000000000000000000000000000000";
    if clk'event and clk='1' then
      case wp is
          when "00"=> s<=p;
          when "01"=> s<=p+h;
          when "10"=> s<=p+g;
          when others=>s<=p;
      end case;
    end if;
  q<=s;
  end process;
end rets;