adderful1.vhd

来自「DDS信号发生器」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adderful1 is
  port( clock:in std_logic;
        wk:in  std_logic_vector(1 downto 0);
        pk :in std_logic_vector(31 downto 0);
         qk:out std_logic_vector(31 downto 0)
     );
 end adderful1;
architecture rets of adderful1 is
component add32
 port( clk:in std_logic;
        a:in  std_logic_vector(31 downto 0);
        b:buffer std_logic_vector(31 downto 0)
      );
end component;
component adderful
 port( clk:in std_logic;
        wp:in  std_logic_vector(1 downto 0);
        p :in std_logic_vector(31 downto 0);
        q:out std_logic_vector(31 downto 0)
     );
end component;
signal m:std_logic_vector(31 downto 0);
begin
 u0:add32 port map(clk=>clock,a=>pk,b=>m);
 u1:adderful port map(clk=>clock,wp=>wk,p=>m,q=>qk);
end rets;