add32.vhd

DDS信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add32 is
  port( clk:in std_logic;
        a:in  std_logic_vector(31 downto 0);
        b:buffer std_logic_vector(31 downto 0)
      );
 end add32;
architecture rt1 of add32 is
signal s:std_logic_vector(31 downto 0);
begin
 process(clk)
 variable pk:std_logic_vector(31 downto 0);
  begin
    pk:="00111111110000000000000000000000";
    if clk'event and clk='1' then
        if s>=pk then
          s<=(others=>'0');
        else
          s<=a+b;
        end if;
    end if;
   b<=s;
  end process;
end rt1;