📄 dds.ptf
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SYSTEM dds
{
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "1";
do_build_sim = "1";
hardcopy_compatible = "0";
board_class = "altera_nios_dev_board_cyclone_1c20";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
display_name = "clk";
Is_Clock_Source = "0";
}
}
hdl_language = "vhdl";
device_family_id = "CYCLONE";
view_master_columns = "1";
view_master_priorities = "0";
name_column_width = "153";
desc_column_width = "153";
bustype_column_width = "0";
base_column_width = "85";
clock_column_width = "80";
end_column_width = "85";
BOARD_INFO
{
CONFIGURATION epcs
{
length = "";
menu_position = "2";
offset = "0x0";
reference_designator = "U59";
}
CONFIGURATION factory
{
length = "";
menu_position = "3";
offset = "0x700000";
reference_designator = "U5";
}
CONFIGURATION user
{
length = "";
menu_position = "1";
offset = "0x600000";
reference_designator = "U5";
}
JTAG_device_index = "1";
REFDES U5
{
base = "0x00800000";
}
REFDES U59
{
base = "0x00060000";
}
altera_avalon_cfi_flash
{
reference_designators = "U5";
}
altera_avalon_epcs_flash_controller
{
reference_designators = "U59";
}
class = "altera_nios_dev_board_cyclone_1c20";
class_version = "6.0";
device_family = "CYCLONE";
quartus_pgm_file = "system/altera_nios_dev_board_cyclone_1c20.sof";
quartus_project_file = "system/altera_nios_dev_board_cyclone_1c20.qpf";
reference_designators = "U59,U5";
sopc_system_file = "system/altera_nios_dev_board_cyclone_1c20.ptf";
}
RESETS
{
RESET reset_n
{
}
}
view_frame_window = "102:96:819:576";
}
}
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