data_rom.tan.rpt

来自「DDS信号发生器」· RPT 代码 · 共 218 行 · 第 1/5 页

; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                      ; To                                                                                                                         ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 3.406 ns                         ; address[5]                                                                                                                ; altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a0~porta_address_reg5 ; --                           ; clock                        ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 7.684 ns                         ; altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|q_a[0]                         ; q[0]                                                                                                                       ; clock                        ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.404 ns                         ; altera_internal_jtag~TDO                                                                                                  ; altera_reserved_tdo                                                                                                        ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.424 ns                         ; altera_internal_jtag~TMSUTAP                                                                                              ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]                                                    ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 189.39 MHz ( period = 5.280 ns ) ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0]                                   ; sld_hub:sld_hub_inst|hub_tdo                                                                                               ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clock'                        ; N/A   ; None          ; 290.87 MHz ( period = 3.438 ns ) ; altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a1~porta_datain_reg3 ; altsyncram:altsyncram_component|altsyncram_9t41:auto_generated|altsyncram_7oi2:altsyncram1|ram_block3a1~porta_memory_reg3  ; clock                        ; clock                        ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                           ;                                                                                                                            ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock                        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;