ddsok.vhd

DDS信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ddsok is
  port(clok:in std_logic;
       wp :in std_logic_vector(1 downto 0);
       fword:in  std_logic_vector(7 downto 0);
       fout:out std_logic_vector(7 downto 0)
     );
 end ddsok;
architecture rt1 of ddsok is
 component adderful1
  port( clock:in std_logic;
        wk:in  std_logic_vector(1 downto 0);
        pk :in std_logic_vector(31 downto 0);
        qk:out std_logic_vector(31 downto 0)
     );
  end component;
 component data_rom
  PORT
	(
		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
  end component;
signal f32b,d32b:std_logic_vector(31 downto 0);
begin
   f32b(27 downto 20)<=fword;
   f32b(31 downto 28)<="0000";
   f32b(19 downto 0)<=(others=>'0');
 u1:adderful1 port map(clock=>clok,wk=>wp,pk=>f32b,qk=>d32b);
 u2:data_rom port map(address=>d32b(31 downto 22),clock=>clok,q=>fout);
end rt1;