adderful1.map.rpt

DDS信号发生器

; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                         ;
+----------------------------------+-----------------+-----------+-----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                  ;
+----------------------------------+-----------------+-----------+-----------------------------------------------+
; adderful1.vhd                    ; yes             ; Other     ; D:/altera/quartus60/program/DDS/adderful1.vhd ;
; add32.vhd                        ; yes             ; Other     ; D:/altera/quartus60/program/DDS/add32.vhd     ;
; adderful.vhd                     ; yes             ; Other     ; D:/altera/quartus60/program/DDS/adderful.vhd  ;
+----------------------------------+-----------------+-----------+-----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 67    ;
;     -- Combinational with no register       ; 3     ;
;     -- Register only                        ; 30    ;
;     -- Combinational with a register        ; 34    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 4     ;
;     -- 3 input functions                    ; 32    ;
;     -- 2 input functions                    ; 1     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 36    ;
;     -- arithmetic mode                      ; 31    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 32    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 64    ;
; Total logic cells in carry chains           ; 32    ;
; I/O pins                                    ; 67    ;
; Maximum fan-out node                        ; clock ;
; Maximum fan-out                             ; 64    ;
; Total fan-out                               ; 272   ;
; Average fan-out                             ; 2.03  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                              ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
; |adderful1                 ; 67 (0)      ; 64           ; 0           ; 0    ; 67   ; 0            ; 3 (0)        ; 30 (0)            ; 34 (0)           ; 32 (0)          ; 0 (0)      ; |adderful1             ;
;    |add32:u0|              ; 35 (35)     ; 32           ; 0           ; 0    ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; 0 (0)      ; |adderful1|add32:u0    ;
;    |adderful:u1|           ; 32 (32)     ; 32           ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 30 (30)           ; 2 (2)            ; 0 (0)           ; 0 (0)      ; |adderful1|adderful:u1 ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 64    ;
; Number of registers using Synchronous Clear  ; 32    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu May 17 19:55:03 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adderful1 -c adderful1
Warning: Using design file adderful1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: adderful1-rets
    Info: Found entity 1: adderful1
Info: Elaborating entity "adderful1" for the top level hierarchy
Warning: Using design file add32.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add32-rt1
    Info: Found entity 1: add32
Info: Elaborating entity "add32" for hierarchy "add32:u0"
Warning (10492): VHDL Process Statement warning at add32.vhd(24): signal "s" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file adderful.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: adderful-rets
    Info: Found entity 1: adderful
Info: Elaborating entity "adderful" for hierarchy "adderful:u1"
Warning (10492): VHDL Process Statement warning at adderful.vhd(27): signal "s" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 134 device resources after synthesis - the final resource count might be different
    Info: Implemented 35 input pins
    Info: Implemented 32 output pins
    Info: Implemented 67 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Thu May 17 19:55:07 2007
    Info: Elapsed time: 00:00:05