port.txt

来自「一个视频信号输入的verilog源代码」· 文本 代码 · 共 14 行

 
 MASTER write_master
       clk_nios    reset_n     m_address     m_write_n     m_writedata     m_waitrequest
       
 SLAVE control_port_slave
       s_address   s_chipselect    s_read_n    s_write_n    s_writedata    s_readdata    
       irq     
       
       
       
       clk_video   clk_cam    cam_clk    cam_din    cam_hsync    cam_vsync