pack565.v

一个视频信号输入的verilog源代码

// ================================================================================
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// ================================================================================
//---------------------------------------------------------------------------
// Output pixel packing
//
// 18 bit RGB pixels are packed to 565 format to reduce memory usage by
// writing two pixels per word.
//---------------------------------------------------------------------------
`timescale 1ns/1ns

module pack565 (
		clk,
		reset_n,
		
		// Input
		rgb_x_en,
		rgb_x_scaled,
		eof_in,
		
		// output
		rgb_packed_en,
		rgb_packed,
		eof
		);

  input clk;
  input reset_n;
  
  // Input
  input rgb_x_en;
  input [17:0] rgb_x_scaled;
  input        eof_in;

  // output
  output       rgb_packed_en;
  output [31:0] rgb_packed;
  output 	eof;

//---------------------------------------------------------------------------
// Dithering could be added here
//---------------------------------------------------------------------------
  wire [15:0] rgb565 = {rgb_x_scaled[17:13],
			rgb_x_scaled[11:6],
			rgb_x_scaled[5:1]};
  
  reg 		word;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      word <= 1'b0;
    else if (eof)
      word <= 1'b0;
    else if (rgb_x_en)
      word <= ~word;
  
  reg [31:0] 	rgb_packed;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      rgb_packed <= 32'b0;
    else if (rgb_x_en & ~word)
      rgb_packed[15:0] <= rgb565;
    else if (rgb_x_en & word)
      rgb_packed[31:16] <= rgb565;

  reg 		rgb_packed_en;
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
      rgb_packed_en <= 1'b0;
    else
      // Send complete words as they are assembled
      // and an extra one if neccessary to complete the line
      rgb_packed_en <= rgb_x_en & word | eof_in & word;
  
  reg  eof_r, eof_rr, eof_rrr, eof;
  // Correct eof for latency through packing and avalon fifo
  always @(posedge clk or negedge reset_n)
    if (~reset_n)
    begin
      eof_r <= 1'b0;
      eof_rr <= 1'b0;
      eof_rrr <= 1'b0;
      eof <= 1'b0;
    end
    else
    begin
      eof_r <= eof_in;
      eof_rr <= eof_r;
      eof_rrr <= eof_rr;
      eof <= eof_rrr;
    end
      
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------

endmodule	// pack565