videoin_harness.v

一个视频信号输入的verilog源代码

// ================================================================================
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// ================================================================================
//---------------------------------------------------------------------------
// Test harness for Auto demo system video-in module
//---------------------------------------------------------------------------
`timescale 1ps/1ps

module aaa_tb ();

  reg reset_n;
  reg clk;

  reg clk_27;

  reg [7:0] input_stimuli [0:1079999];

  // Camera
  reg 	    cam_clk;
  reg [7:0] cam_din;
  reg 	    cam_hsync;
  reg 	    cam_vsync;

  // Avalon DMA master
  wire [31:0] m_address;
  wire 	      m_write_n;
  wire [31:0] m_writedata;
  reg 	      m_waitrequest;

   // Avalon DMA register slave
  reg [4:0]   s_address;
  reg 	      s_chipselect;
  reg 	      s_read_n;
  reg 	      s_write_n;
  reg [31:0]  s_writedata;
  wire [31:0] s_readdata;

//---------------------------------------------------------------------------
// Clocks
//---------------------------------------------------------------------------
  // 100MHz system clock
  initial begin
    clk = 1'b0;
    while (1) #5000 clk = ~clk;
  end
  
  // 26MHz video in clock
  initial begin
    clk_27 = 1'b0;
    while (1) #19231 clk_27 = ~clk_27;
  end

  integer line;
  integer pixel;
  reg [7:0] y_in;
  reg [7:0] cb_in;
  reg [7:0] cr_in;
  
  initial
    begin
      cam_clk = 1'b0;
      cam_din = {8{1'bx}};
      cam_hsync = 1'b0;
      cam_vsync = 1'b0;
      s_address = 5'b0;
      s_chipselect = 1'b0;
      s_read_n = 1'b0;
      s_write_n = 1'b1;
      s_writedata = 32'b0;
      reset_n = 1'b0;
      repeat(5) @(negedge clk_27);
      #1 reset_n = 1'b1;
      repeat(5) @(negedge clk_27);





      s_chipselect = 1'b1;
      // Set up camera xlen
      avalon_write(7'h10>>2, 32'd639);
      
      @(posedge clk);
      // Set up xclips
      avalon_write(7'h20>>2, 32'd1);
      
      @(posedge clk);
      // Set up xclipe
      avalon_write(7'h24>>2, 32'd10);
      
      @(posedge clk);
      // Set up yclips
      avalon_write(7'h28>>2, 32'd1);
      
      @(posedge clk);
      // Set up yclipe
      avalon_write(7'h2c>>2, 32'd10);
      
      @(posedge clk);
      // Set up xscale
      avalon_write(7'h30>>2, 32'h0c00);
      
      @(posedge clk);
      // Set up xlen
      avalon_write(7'h34>>2, 32'd9);
      
      @(posedge clk);
      // Set up yscale
      avalon_write(7'h38>>2, 32'h0c00);
      
      @(posedge clk);
      // Set up ylen
      avalon_write(7'h3c>>2, 32'd9);
      
      @(posedge clk);
      // Set up mfb
      avalon_write(7'h50>>2, 32'h10000);
      









/* -----\/----- EXCLUDED -----\/-----
      s_chipselect = 1'b1;
      // Set up camera xlen
      avalon_write(7'h10>>2, 32'd639);
      
      @(posedge clk);
      // Set up xclips
      avalon_write(7'h20>>2, 32'd420);
      
      @(posedge clk);
      // Set up xclipe
      avalon_write(7'h24>>2, 32'd639);
      
      @(posedge clk);
      // Set up yclips
      avalon_write(7'h28>>2, 32'd320);
      
      @(posedge clk);
      // Set up yclipe
      avalon_write(7'h2c>>2, 32'd479);
      
      @(posedge clk);
      // Set up xscale
      avalon_write(7'h30>>2, 32'h0555);
      
      @(posedge clk);
      // Set up xlen
      avalon_write(7'h34>>2, 32'd219);
      
      @(posedge clk);
      // Set up yscale
      avalon_write(7'h38>>2, 32'h0555);
      
      @(posedge clk);
      // Set up ylen
      avalon_write(7'h3c>>2, 32'd159);
      
      @(posedge clk);
      // Set up mfb
      avalon_write(7'h50>>2, 32'h100000);
      
 -----/\----- EXCLUDED -----/\----- */
      






      @(posedge clk);
      // Set up mcontrol
      avalon_write(7'h40>>2, 32'd1);
      s_chipselect = 1'b0;
      
      repeat(10) @(posedge clk);

      fork
	begin
	  repeat(10) @(negedge clk_27);
	  #1 cam_vsync = 1'b1;
	  cb_in = 8'd16;
	  cr_in = 8'd32;
	  y_in = 8'd0;
	  for (line = 1; line <= 480; line = line + 1)
	  begin
	    cam_hsync = 1'b1;
	    for (pixel = 1; pixel <= 640; pixel = pixel + 2)
	    begin
	      #1 cam_din = cb_in;
	      @(posedge clk_27);
	      #1 cam_clk = 1'b1;
	      @(negedge clk_27);
	      #1 cam_clk = 1'b0;
	      cam_din = y_in;
	      @(posedge clk_27);
	      #1 cam_clk = 1'b1;
	      @(negedge clk_27);
	      #1 cam_clk = 1'b0;
	      cam_din = cr_in;
	      y_in = y_in + 1;
	      @(posedge clk_27);
	      #1 cam_clk = 1'b1;
	      @(negedge clk_27);
	      #1 cam_clk = 1'b0;
	      cam_din = y_in;
	      @(posedge clk_27);
	      #1 cam_clk = 1'b1;
	      @(negedge clk_27);
	      #1 cam_clk = 1'b0;
	      cb_in = cb_in + 1;
	      cr_in = cr_in + 1;
	      y_in = y_in + 1;
	    end
	    cam_hsync = 1'b0;
	    for (pixel = 641; pixel <= 846; pixel = pixel + 1)
	      @(negedge clk_27);
	  end
	  #1 cam_vsync = 1'b0;
	  for (line = 481; line <= 512; line = line + 1)
	    for (pixel = 1; pixel <= 846; pixel = pixel + 1)
	      @(posedge clk_27);
	end
      join

      // wait for h_blank
      repeat(20) @(posedge clk_27);

      $finish;
      
    end

  task avalon_write;
    input [4:0] address;
    input [31:0] data;
    begin
      @(posedge clk);
      #1 s_writedata = data;
      s_address = address;
      s_write_n = 1'b0;
      @(posedge clk);
      #1 s_write_n = 1'b1;
    end
  endtask
  
//---------------------------------------------------------------------------
// Instantiate video input module
//---------------------------------------------------------------------------
  videoin dut (
	       .reset_n		(reset_n),
	       .clk_nios	(clk),
	       .clk_video	(clk),
	       .clk_27		(clk_27),

	       // camera interface
	       .cam_clk		(cam_clk),
	       .cam_din		(cam_din),
	       .cam_hsync	(cam_hsync),
	       .cam_vsync	(cam_vsync),
		
	       // Avalon DMA register slave
	       .s_address	(s_address),
	       .s_chipselect	(s_chipselect),
	       .s_read_n	(s_read_n),
	       .s_write_n	(s_write_n),
	       .s_writedata	(s_writedata),
	       .s_readdata	(s_readdata),
		
	       // Avalon DMA master
	       .m_address	(m_address),
	       .m_write_n	(m_write_n),
	       .m_writedata	(m_writedata),
	       .m_waitrequest	(1'b0)
	       );

  

endmodule